lpc177x_8x_emc.h

NXPl788上lwip的无操作系统移植,基于Embest开发板

/**********************************************************************
* $Id$		lpc177x_8x_emc.h			2011-06-02
*//**
* @file		lpc177x_8x_emc.h
* @brief	Contains all macro definitions and function prototypes
*			support for EMC firmware library on LPC177x_8x
* @version	1.0
* @date		02. June. 2011
* @author	NXP MCU SW Application Team
* 
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers.  This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/

/* Peripheral group ----------------------------------------------------------- */
/** @defgroup EMC	EMC (External Memory Controller)
 * @ingroup LPC177x_8xCMSIS_FwLib_Drivers
 * @{
 */

#ifndef __LPC177X_8X_EMC_H_
#define __LPC177X_8X_EMC_H_

#include "lpc_types.h"
#include "LPC177x_8x.h"


/** @defgroup EMC_Private_Macros EMC Private Macros
 * @{
 */

/***********************************************************************
 * EMC Control Register (EMCControl)
 **********************************************************************/
/* Control register mask */
#define EMC_Control_MASK			((uint32_t )0x07)
/* Control register EMC: Enable control. */
#define EMC_Control_E				((uint32_t )(1<<0))
/* Control register EMC: Address mirror control. */
#define EMC_Control_M				((uint32_t )(1<<1))
/* Control register EMC: Low-power mode control. */
#define EMC_Control_L				((uint32_t )(1<<2))

/***********************************************************************
 * EMC Status Register (EMCStatus)
 **********************************************************************/
/* Status register mask */
#define EMC_Status_MASK				((uint32_t )0x07)
/* Status register EMC: Busy. */
#define EMC_Status_B				((uint32_t )(1<<0))
/* Status register EMC: Write buffer status. */
#define EMC_Status_S				((uint32_t )(1<<1))
/* Status register EMC: Self-refresh acknowledge.. */
#define EMC_Status_SA				((uint32_t )(1<<2))

/***********************************************************************
 * EMC Configuration register (EMCConfig)
 **********************************************************************/
/* EMC Configuration register : Little Endian. */
#define EMC_Config_Little_Endian_Mode		((uint32_t )(0<<0))
/* EMC Configuration register : Big Endian. */
#define EMC_Config_Big_Endian_Mode		((uint32_t )(1<<0))
/* EMC Configuration: Endian Mask */
#define EMC_Config_Endian_Mask           (0x01<<0)

/* EMC Configuration register: CLKOUT ratio 1:1. */
#define EMC_Config_CCLK_1_1				((uinr32_t)(0<<8))
/* EMC Configuration register: CLKOUT ratio 1:1. */
#define EMC_Config_CCLK_1_2				((uinr32_t)(1<<8))

/* EMC Configuration register mask */
#define EMC_Config_MASK				((uint32_t)(0x101))


/***********************************************************************
 * Dynamic Memory Control register (EMCDynamicControl)
 **********************************************************************/
/* Dynamic Memory Control register EMC: Dynamic memory clock enable. */
#define EMC_DYNAMIC_CTRL_MEMCLK_EN_POS				(0)
#define EMC_DYNAMIC_CTRL_MEMCLK_EN_BMASK			(1<<EMC_DYNAMIC_CTRL_MEMCLK_EN_POS)

#define EMC_DYNAMIC_CTRL_CE_SAVEPWR				(0<<EMC_DYNAMIC_CTRL_MEMCLK_EN_POS)
#define EMC_DYNAMIC_CTRL_CE_ALLCLK_HI				(1<<EMC_DYNAMIC_CTRL_MEMCLK_EN_POS)

/* Dynamic Memory Control register EMC: Dynamic memory clock control */
#define EMC_DYNAMIC_CTRL_CLKCTRL_POS				(1)
#define EMC_DYNAMIC_CTRL_CLKCTRL_BMASK				(1<<EMC_DYNAMIC_CTRL_CLKCTRL_POS)

#define EMC_DYNAMIC_CTRL_CS_CLKOUT_STOP				(0<<EMC_DYNAMIC_CTRL_CLKCTRL_POS)
#define EMC_DYNAMIC_CTRL_CE_CLKOUT_CONT				(1<<EMC_DYNAMIC_CTRL_CLKCTRL_POS)

/* Dynamic Memory Control register EMC: Self-refresh request, EMCSREFREQ*/
#define EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_POS			(2)
#define EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_BMASK			(1<<EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_POS)

#define EMC_DYNAMIC_CTRL_SR_NORMALMODE				(0<<EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_POS)
#define EMC_DYNAMIC_CTRL_SR_SELFREFRESH				(1<<EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_POS)

/* Dynamic Memory Control register EMC: Memory clock control (MMC)*/
#define EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_POS			(5)
#define EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_BMASK			(1<<EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_POS)

#define EMC_DYNAMIC_CTRL_MMC_CLKOUT_ENABLED			(0<<EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_POS)
#define EMC_DYNAMIC_CTRL_MMC_CLKOUT_DISABLED			(1<<EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_POS)


/* Dynamic Memory Control register EMC: SDRAM initialization*/
#define EMC_DYNAMIC_CTRL_SDRAM_INIT_POS				(7)
#define EMC_DYNAMIC_CTRL_SDRAM_INIT_BMASK			(0x03<<EMC_DYNAMIC_CTRL_SDRAM_INIT_POS)

#define EMC_DYNAMIC_CTRL_SDRAM_NORMAL				(0<<EMC_DYNAMIC_CTRL_SDRAM_INIT_POS)
#define EMC_DYNAMIC_CTRL_SDRAM_MODE				(1<<EMC_DYNAMIC_CTRL_SDRAM_INIT_POS)
#define EMC_DYNAMIC_CTRL_SDRAM_PALL				(2<<EMC_DYNAMIC_CTRL_SDRAM_INIT_POS)
#define EMC_DYNAMIC_CTRL_SDRAM_NOP				(3<<EMC_DYNAMIC_CTRL_SDRAM_INIT_POS)

/* Dynamic Memory Control register EMC: Low-power SDRAM deep-sleep mode (DP)*/
#define EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_POS			(13)
#define EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_BMASK			(0x01<<EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_POS)

#define EMC_DYNAMIC_CTRL_DP_NORMAL				(0<<EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_POS)
#define EMC_DYNAMIC_CTRL_DP_DEEPSLEEP				(1<<EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_POS)


/***********************************************************************
 * Dynamic Memory Refresh Timer register (EMCDynamicRefresh)
 **********************************************************************/
/* Dynamic Memory Refresh Timer register EMC: Refresh timer (REFRESH) */
#define EMC_DynamicRefresh_REFRESH(n)	((uint32_t ) (n & 0x3ff))

/***********************************************************************
 * Dynamic Memory Read Configuration register (EMCDynamicReadConfig)
 **********************************************************************/
/* EMCDynamicReadConfig register EMC:Read data strategy (RD) */
#define EMC_DynamicReadConfig_RD(n)		((uint32_t )(n & 0x03))

/***********************************************************************
 * Dynamic Memory Percentage Command Period register (EMCDynamictRP)
 **********************************************************************/
/* EMCDynamictRP register EMC: Precharge command period (tRP). */
#define EMC_DynamictRP_tRP(n)			((uint32_t )(n & 0x0f))

/***********************************************************************
 * Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS)
 **********************************************************************/
/* EMCDynamictRAS register EMC: Active to precharge command period (tRAS) */
#define EMC_DynamictRP_tRAS(n)			((uint32_t )(n & 0x0f))

/***********************************************************************
 * Dynamic Memory Self-refresh Exit Time register (EMCDynamictSREX)
 **********************************************************************/
/* EMCDynamictSREX register EMC: self-refresh exit time (tSREX)) */

#define EMC_DynamictRP_tSREX(n)			((uint32_t )(n & 0x0f))

/***********************************************************************
 * Dynamic Memory Last Data Out to Active Time register (EMCDynamictAPR)
 **********************************************************************/
/* EMCDynamictAPR register EMC: Last-data-out to active command time (tAPR) */
#define EMC_DynamictAPR_tAPR(n)			((uint32_t )(n & 0x0f))

/***********************************************************************
 * Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL)
 **********************************************************************/
/* EMCDynamictDAL register EMC: Data-in to active command (tDAL)*/
#define EMC_DynamictDAL_tDAL(n)			((uint32_t )(n & 0x0f))

/***********************************************************************
 * Dynamic Memory Write Recovery Time register (EMCDynamictWR)
 **********************************************************************/
/* EMCDynamictWR register EMC: Write recovery time (tWR)*/
#define EMC_DynamictWR_tWR(n)			(uint32_t )(n & 0x0f)

/***********************************************************************
 * Dynamic Memory Active to Active Command Period register (EMCDynamictRC)
 **********************************************************************/
/* EMCDynamictRC register EMC: Active to active command period (tRC)*/
#define EMC_DynamictRC_tRC(n)			(uint32_t )(n & 0x1f)

/***********************************************************************
 * Dynamic Memory Auto-refresh Period register (EMCDynamictRFC)
 **********************************************************************/
/* EMCDynamictRFC register EMC: Auto-refresh period and auto-refresh to active command period (tRFC)*/
#define EMC_DynamictRFC_tRFC(n)			((uint32_t )(n & 0x1f))

/***********************************************************************
 * Dynamic Memory Exit Self-refresh register (EMCDynamictXSR)
 **********************************************************************/
/* EMCDynamictXSR register EMC: Exit self-refresh to active command time (tXSR)*/
#define EMC_DynamictXSR_tXSR(n)			((uint32_t )(n & 0x1f))

/***********************************************************************
 * Dynamic Memory Active Bank A to Active Bank B Time register (EMCDynamictRRD)
 **********************************************************************/
/* EMCDynamictRRD register EMC: Active bank A to active bank B latency (tRRD )*/
#define EMC_DynamictRRD_tRRD(n)			((uint32_t )(n & 0x0f))

/***********************************************************************
 Dynamic Memory Load Mode register to Active Command Time (EMCDynamictMRD)
 **********************************************************************/
/* EMCDynamictMRD register EMC: Load mode register to active command time (tMRD)*/
#define EMC_DynamictMRD_tMRD(n)			((uint32_t )(n & 0x1f))

/***********************************************************************
 * Static Memory Extended Wait Register (EMCStaticExtendedWait)
 **********************************************************************/
/* StaticExtendedWait register EMC: External wait time out. */
#define EMC_StaticExtendedWait_EXTENDEDWAIT(n)			((uint32_t )(n & 0x3ff))


/***********************************************************************
 * Dynamic Memory Configuration registers (EMCDynamicConfig0-3)
 **********************************************************************/
/* DynamicConfig register EMC: Memory device (MD). */
#define EMC_DYNAMIC_CFG_MEMDEV_POS				(3)
#define EMC_DYNAMIC_CFG_MEMDEV_BMASK				(0x03 << EMC_DYNAMIC_CFG_MEMDEV_POS)

#define EMC_DYNAMIC_CFG_MEMDEV_SDRAM				(0 << EMC_DYNAMIC_CFG_MEMDEV_POS)
#define EMC_DYNAMIC_CFG_MEMDEV_LOWPWR_SDRAM			(1 << EMC_DYNAMIC_CFG_MEMDEV_POS)

/* DynamicConfig register EMC: Address mapping (AM) */
#define EMC_DYNAMIC_CFG_ADD_MAP_P1_POS				(7)
#define EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK                   	(0x3F<<EMC_DYNAMIC_CFG_ADD_MAP_P1_POS)
#define EMC_DYNAMIC_CFG_ADD_MAP_P2_POS                      	(12)
#define EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK                   	(0x01 << EMC_DYNAMIC_CFG_ADD_MAP_P2_POS)
#define EMC_DYNAMIC_CFG_ADD_MAP_P3_POS                      	(14)
#define EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK                   	(0x01 << EMC_DYNAMIC_CFG_ADD_MAP_P3_POS)

#define EMC_DYNAMIC_CFG_ADD_MAP_P1(n)                         (  (n<<EMC_DYNAMIC_CFG_ADD_MAP_P1_POS)&EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK)
#define EMC_DYNAMIC_CFG_ADD_MAP_P2(n)                         (  (n<<EMC_DYNAMIC_CFG_ADD_MAP_P2_POS)&EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK)
#define EMC_DYNAMIC_CFG_ADD_MAP_P3(n)                         (  (n<<EMC_DYNAMIC_CFG_ADD_MAP_P3_POS)&EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK)

#define EMC_ADD_MAP_ROW_BANK_COL                               (0)
#define EMC_ADD_MAP_BANK_ROW_COL                               (1)


/* DynamicConfig register EMC: Buffer enable */
#define EMC_DYNAMIC_CFG_BUFFENABLE_POS			(19)
#define EMC_DYNAMIC_CFG_BUFFENABLE_BMASK		(0x01<<EMC_DYNAMIC_CFG_BUFFENABLE_POS)

#define EMC_DYNAMIC_CFG_BUFF_DISABLED			(0<<EMC_DYNAMIC_CFG_BUFFENABLE_POS)
#define EMC_DYNAMIC_CFG_BUFF_ENABLED			(1<<EMC_DYNAMIC_CFG_BUFFENABLE_POS)


/* DynamicConfig register EMC: Write protect (P) */
#define EMC_DYNAMIC_CFG_WRPROTECT_POS			(20)
#define EMC_DYNAMIC_CFG_WRPROTECT_BMASK			(0x01<<EMC_DYNAMIC_CFG_WRPROTECT_POS)

#define EMC_DYNAMIC_CFG_WR_UNPROTECTED			(0<<EMC_DYNAMIC_CFG_WRPROTECT_POS)
#define EMC_DYNAMIC_CFG_WR_PROTECTED			(1<<EMC_DYNAMIC_CFG_WRPROTECT_POS)

/***********************************************************************
 * Dynamic Memory RAS & CAS Delay registers (EMCDynamicRASCAS0-3)
 **********************************************************************/
/* DynamicRASCAS register EMC: RAS latency (active to read/write delay) (RAS). */
#define EMC_DYNAMIC_RASCAS_RASCFG_POS			(0)
#define EMC_DYNAMIC_RASCAS_RASCFG_BMASK			(0x03<<EMC_DYNAMIC_RASCAS_RASCFG_POS)