📄 lpc177x_8x_emac.h
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#define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
#define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
#define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
/* Power Down Register */
#define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
/* Descriptor and status formats ------------------------------------------------------ */
/* RX and TX descriptor and status definitions. */
/* EMAC Memory Buffer configuration for 16K Ethernet RAM */
#define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
#define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
#define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
#define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
/* EMAC variables located in 16K Ethernet SRAM */
#define RX_DESC_BASE LPC_PERI_RAM_BASE
#define RX_STAT_BASE (RX_DESC_BASE + EMAC_NUM_RX_FRAG*8)
#define TX_DESC_BASE (RX_STAT_BASE + EMAC_NUM_RX_FRAG*8)
#define TX_STAT_BASE (TX_DESC_BASE + EMAC_NUM_TX_FRAG*8)
#define RX_BUF_BASE (TX_STAT_BASE + EMAC_NUM_TX_FRAG*4)
#define TX_BUF_BASE (RX_BUF_BASE + EMAC_NUM_RX_FRAG*EMAC_ETH_MAX_FLEN)
/**
* @brief RX Descriptor structure type definition
*/
#define RX_DESC_PACKET(i) (*(uint32_t *)(RX_DESC_BASE + 8*i))
#define RX_DESC_CTRL(i) (*(uint32_t *)(RX_DESC_BASE+4 + 8*i))
/**
* @brief RX Status structure type definition
*/
#define RX_STAT_INFO(i) (*(uint32_t *)(RX_STAT_BASE + 8*i))
#define RX_STAT_HASHCRC(i) (*(uint32_t *)(RX_STAT_BASE+4 + 8*i))
/**
* @brief TX Descriptor structure type definition
*/
#define TX_DESC_PACKET(i) (*(uint32_t *)(TX_DESC_BASE + 8*i))
#define TX_DESC_CTRL(i) (*(uint32_t *)(TX_DESC_BASE+4 + 8*i))
/**
* @brief TX Status structure type definition
*/
#define TX_STAT_INFO(i) (*(uint32_t *)(TX_STAT_BASE + 4*i))
/**
* @brief TX Data Buffer structure definition
*/
#define RX_BUF(i) (RX_BUF_BASE + EMAC_ETH_MAX_FLEN*i)
#define TX_BUF(i) (TX_BUF_BASE + EMAC_ETH_MAX_FLEN*i)
/* RX Descriptor Control Word */
#define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
#define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
/* RX Status Hash CRC Word */
#define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
#define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
/* RX Status Information Word */
#define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
#define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
#define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
#define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
#define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
#define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
#define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
#define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
#define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
#define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
#define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
#define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
#define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
#define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
#define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
/** RX Status Information word mask */
#define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
/* TX Descriptor Control Word */
#define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
#define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
#define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
#define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
#define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
#define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
#define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
/* TX Status Information Word */
#define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
#define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
#define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
#define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
#define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
#define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
#define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
#define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
/* DP83848C PHY definition ------------------------------------------------------------ */
/** PHY device reset time out definition */
#define EMAC_PHY_RESP_TOUT 0x100000UL
/* ENET Device Revision ID */
#define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
/* PHY Basic Mode Control Register (BMCR) bitmap definitions */
#define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
//#define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
#define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
#define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
#define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
#define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
#define EMAC_PHY_FULLD_100M (EMAC_PHY_BMCR_SPEED_SEL | EMAC_PHY_BMCR_DUPLEX) // Full Duplex 100Mbit
#define EMAC_PHY_HALFD_100M (EMAC_PHY_BMCR_SPEED_SEL | (~ EMAC_PHY_BMCR_DUPLEX)) // Half Duplex 100Mbit
#define EMAC_PHY_FULLD_10M ((~ EMAC_PHY_BMCR_SPEED_SEL) | EMAC_PHY_BMCR_DUPLEX) // Full Duplex 10Mbit
#define EMAC_PHY_HALFD_10M ((~ EMAC_PHY_BMCR_SPEED_SEL) | (~EMAC_PHY_BMCR_DUPLEX)) // Half Duplex 10MBit
#define EMAC_PHY_AUTO_NEG (EMAC_PHY_BMCR_SPEED_SEL | EMAC_PHY_BMCR_AN) // Select Auto Negotiation
/* EMAC PHY status type definitions */
#define EMAC_PHY_STAT_LINK (0) /**< Link Status */
#define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
#define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
/* EMAC PHY device Speed definitions */
#define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
#define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
#define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
#define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
#define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
/* EMAC User Buffers*/
#define EMAC_MAX_FRAME_SIZE (0x600) /* 1536 */
#define EMAC_MAX_FRAME_NUM (2)
/* EMAC Error Codes */
#define EMAC_ALIGN_ERR ( 1 << 0)
#define EMAC_RANGE_ERR ( 1 << 1)
#define EMAC_LENGTH_ERR ( 1 << 2)
#define EMAC_SYMBOL_ERR ( 1 << 3)
#define EMAC_CRC_ERR ( 1 << 4)
#define EMAC_RX_NO_DESC_ERR ( 1 << 5)
#define EMAC_OVERRUN_ERR ( 1 << 6)
#define EMAC_LATE_COLLISION_ERR ( 1 << 7)
#define EMAC_EXCESSIVE_COLLISION_ERR ( 1 << 8)
#define EMAC_EXCESSIVE_DEFER_ERR ( 1 << 9)
#define EMAC_UNDERRUN_ERR ( 1 << 10)
#define EMAC_TX_NO_DESC_ERR ( 1 << 11)
#define EMAC_FILTER_FAILED_ERR ( 1 << 12)
/**
* @}
*/
/**************************** GLOBAL/PUBLIC TYPES ***************************/
/** @defgroup EMAC_Public_Types EMAC Public Types
* @{
*/
/**
* @brief TX Data Buffer structure definition
*/
typedef struct {
uint32_t ulDataLen; /**< Data length */
uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
} EMAC_PACKETBUF_Type;
/**
* @brief PHY Configuration structure definition
*/
typedef struct {
uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
- EMAC_MODE_AUTO
- EMAC_MODE_10M_FULL
- EMAC_MODE_10M_HALF
- EMAC_MODE_100M_FULL
- EMAC_MODE_100M_HALF
*/
} EMAC_PHY_CFG_Type;
/** EMAC Call back function type definition */
typedef int32_t (PHY_INIT_FUNC)(EMAC_PHY_CFG_Type* pPhyCfg);
typedef int32_t (PHY_RESET_FUNC)(void);
typedef void (EMAC_FRAME_RECV_FUNC)(uint16_t* pData, uint32_t size);
typedef void (EMAC_TRANSMIT_FINISH_FUNC)(void);
typedef void (EMAC_ERR_RECV_FUNC)(int32_t ulErrCode);
typedef void (EMAC_WAKEUP_FUNC)(void);
typedef void (SOFT_INT_FUNC)(void);
/**
* @brief EMAC configuration structure definition
*/
typedef struct {
EMAC_PHY_CFG_Type PhyCfg; /* PHY Configuration */
uint8_t bPhyAddr; /* 5-bit PHY Address field */
uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
*/
uint16_t nMaxFrameSize; /* maximum frame length */
PHY_INIT_FUNC *pfnPHYInit; /* point to the funtion which will be called to initialize PHY */
PHY_RESET_FUNC *pfnPHYReset; /* point to the function which will be called to reset PHY */
EMAC_FRAME_RECV_FUNC *pfnFrameReceive; /* point to the function which will be called when a frame is received*/
EMAC_TRANSMIT_FINISH_FUNC* pfnTransmitFinish; /*point to the function which will be called when transmit finished*/
EMAC_ERR_RECV_FUNC *pfnErrorReceive; /* point to an array of functions which will be called error occur. */
/* Errors:
EMAC_ALIGN_ERR
EMAC_RANGE_ERR
EMAC_LENGTH_ERR
EMAC_SYMBOL_ERR
EMAC_CRC_ERR
EMAC_RX_NO_DESC_ERR
EMAC_OVERRUN_ERR
EMAC_LATE_COLLISION_ERR
EMAC_EXCESSIVE_COLLISION_ERR
EMAC_EXCESSIVE_DEFER_ERR
EMAC_UNDERRUN_ERR
EMAC_TX_NO_DESC_ERR
*/
EMAC_WAKEUP_FUNC *pfnWakeup; /* point to the function which will be called when receiving wakeup interrupt */
SOFT_INT_FUNC *pfnSoftInt; /* point to the function which will be called when the interrupt caused by software occurs */
} EMAC_CFG_Type;
/**
* @brief EMAC Buffer status definition
*/
typedef enum {
EMAC_BUFF_EMPTY, /* buffer is empty */
EMAC_BUFF_PARTIAL_FULL, /* buffer contains some packets */
EMAC_BUFF_FULL, /* buffer is full */
} EMAC_BUFF_STATUS;
/**
* @brief EMAC Buffer Index definition
*/
typedef enum {
EMAC_TX_BUFF, /* transmit buffer */
EMAC_RX_BUFF, /* receive buffer */
} EMAC_BUFF_IDX;
/**
* @}
*/
/** @defgroup EMAC_Public_Functions EMAC Public Functions
* @{
*/
/** Init/DeInit */
int32_t EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
void EMAC_DeInit(void);
/** Send/Receive data */
void EMAC_TxEnable( void );
void EMAC_RxEnable( void );
void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState);
int32_t EMAC_CRCCalc(uint8_t frame_no_fcs[], int32_t frame_len);
void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
/** PHY Setup */
void EMAC_Write_PHY (uint8_t PhyReg, uint16_t Value);
uint16_t EMAC_Read_PHY (uint8_t PhyReg);
void EMAC_SetFullDuplexMode(uint8_t full_duplex);
void EMAC_SetPHYSpeed(uint8_t mode_100Mbps);
/** Filter */
void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState);
FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode);
void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState);
IntStatus EMAC_IntGetStatus(uint32_t ulIntType);
EMAC_BUFF_STATUS EMAC_GetBufferSts(EMAC_BUFF_IDX idx);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __LPC177X_8X_EMAC_DRIVER_H_ */
/**
* @}
*/
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