📄 autoboot-1.3.0.patch
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+ *addr = INTEL_CONFIRM; /* clear */+ } - if (addr & 1) {- printf ("unaligned destination not supported\n");- return ERR_ALIGN;- };-- if ((int) src & 1) {- printf ("unaligned source not supported\n");- return ERR_ALIGN;- };-- wp = addr;-- while (cnt >= 2) {- data = *((volatile u16 *) src);- if ((rc = write_word (info, wp, data)) != 0) {- return (rc);+ reset_timer_masked ();++ while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {+ if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) {+ printf("Flash lock bit operation timed out\n");+ rc = 1;+ break; }- src += 2;- wp += 2;- cnt -= 2; } - if (cnt == 1) {- data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) <<- 8);- if ((rc = write_word (info, wp, data)) != 0) {- return (rc);+ if (*addr != INTEL_OK) {+ printf("Flash lock bit operation failed at %08X, CSR=%08X\n",+ (uint)addr, (uint)*addr);+ rc = 1;+ }++ if (!rc)+ info->protect[sector] = prot;++ /*+ * Clear lock bit command clears all sectors lock bits, so+ * we have to restore lock bits of protected sectors.+ */+ if (!prot)+ {+ for (i = 0; i < info->sector_count; i++)+ {+ if (info->protect[i])+ {+ reset_timer_masked ();+ addr = (vu_long *)(info->start[i]);+ *addr = INTEL_LOCKBIT; /* Sector lock bit */+ *addr = INTEL_PROTECT; /* set */+ while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)+ {+ if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT)+ {+ printf("Flash lock bit operation timed out\n");+ rc = 1;+ break;+ }+ }+ } }- src += 1;- wp += 1;- cnt -= 1;- };+ }++ if (flag)+ enable_interrupts(); - return ERR_OK;+ *addr = INTEL_RESET; /* Reset to read array mode */++ return rc; }diff -urN u-boot-1.3.0.orig/cpu/arm920t/config.mk u-boot-1.3.0/cpu/arm920t/config.mk--- u-boot-1.3.0.orig/cpu/arm920t/config.mk 2007-11-28 11:52:24.000000000 +0800+++ u-boot-1.3.0/cpu/arm920t/config.mk 2008-03-18 15:11:55.000000000 +0800@@ -24,7 +24,7 @@ PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ -msoft-float -PLATFORM_CPPFLAGS += -march=armv4+PLATFORM_CPPFLAGS += -march=armv4t # ========================================================================= # # Supply options according to compiler versiondiff -urN u-boot-1.3.0.orig/cpu/arm920t/start.S u-boot-1.3.0/cpu/arm920t/start.S--- u-boot-1.3.0.orig/cpu/arm920t/start.S 2007-11-28 11:52:24.000000000 +0800+++ u-boot-1.3.0/cpu/arm920t/start.S 2008-03-18 15:11:55.000000000 +0800@@ -120,12 +120,35 @@ bl red_LED_on #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)+ mov r0, #0x55+ ldr r1, =0x0+ str r0, [r1]+ ldr r2, [r1]+ cmp r2, r0+ beq 1f+ adr r0, _start+ ldr r1, _TEXT_BASE+ cmp r0, r1+ beq 2f+ bne 3f+1: /* * relocate exception table */+ mov r11, #0x00 ldr r0, =_start ldr r1, =0x0 mov r2, #16+ b copyex+2:+ ldr r0, =_start+ b 4f+3:+ ldr r0, =0x10000000+4:+ mov r11, #0x01+ mov r2, #16+ ldr r1, =0x00200000 copyex: subs r2, r2, #1 ldr r3, [r0], #4@@ -262,10 +285,13 @@ */ mov ip, lr #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) || defined(CONFIG_AT91RM9200DF)--#else- bl lowlevel_init+ adr r0, _start+ ldr r1, _TEXT_BASE+ cmp r0, r1+ beq 1f #endif+ bl lowlevel_init+1: mov lr, ip mov pc, lr #endif /* CONFIG_SKIP_LOWLEVEL_INIT */diff -urN u-boot-1.3.0.orig/include/common.h u-boot-1.3.0/include/common.h--- u-boot-1.3.0.orig/include/common.h 2007-11-28 11:52:25.000000000 +0800+++ u-boot-1.3.0/include/common.h 2008-03-18 15:11:55.000000000 +0800@@ -657,4 +657,7 @@ #error Read section CONFIG_SKIP_LOWLEVEL_INIT in README. #endif +#define MEM_READ(addr) (*(volatile unsigned long *)(addr))+#define MEM_WRITE(addr, val) (*(volatile unsigned long *)(addr) = (val))+ #endif /* __COMMON_H_ */diff -urN u-boot-1.3.0.orig/include/configs/at91rm9200dk.h u-boot-1.3.0/include/configs/at91rm9200dk.h--- u-boot-1.3.0.orig/include/configs/at91rm9200dk.h 2007-11-28 11:52:24.000000000 +0800+++ u-boot-1.3.0/include/configs/at91rm9200dk.h 2008-03-23 08:12:23.000000000 +0800@@ -28,16 +28,21 @@ /* ARM asynchronous clock */ #define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ #define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */-/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */ +/* ARM Slow Clock */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ +/* SoC and Board */ #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ #define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ #define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define USE_920T_MMU 1 +/* added by lqm */+#undef CONFIG_REMAP_TEST /* print 0x000000-0x000040 */++/* set the tag list */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1@@ -54,7 +59,7 @@ #define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ /* clocks */-#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */+#define PLLAR_VAL 0x2026BE04 /* 179.712000 MHz for PCK */ #define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ #define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ @@ -73,6 +78,7 @@ #define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */+ /* * Size of malloc() pool */@@ -89,14 +95,20 @@ #define CONFIG_DBGU #undef CONFIG_USART0 #undef CONFIG_USART1- #undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */- #undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ #define CONFIG_BOOTDELAY 3-/* #define CONFIG_ENV_OVERWRITE 1 */-+#define CONFIG_BOOTARGS "noinitrd root=/dev/mtdblock3 rw rootfstype=jffs2 console=ttySAC0,115200 mem=32M"+#define CONFIG_BOOTCOMMAND "cp.b 10020000 21000000 120000\;bootm 21000000"+#if 0+#define CONFIG_ETHADDR 36:B9:04:00:24:80+#define CONFIG_NETMASK 255.255.255.0+#define CONFIG_IPADDR 192.168.1.100+#define CONFIG_SERVERIP 192.168.1.106+#define CONFIG_BOOTFILE "rootfs.jffs2"+#define CONFIG_BOOTCOMMAND "tftp 21000000 rootfs.jffs2\;bootm 21000000"+#endif /* * BOOTP options@@ -106,52 +118,22 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration.+ * You need to modify the [include/config_cmd_default.h] to customize the default commands. */ #include <config_cmd_default.h> #define CONFIG_CMD_MII #define CONFIG_CMD_DHCP+#define CONFIG_CMD_PING #undef CONFIG_CMD_BDI #undef CONFIG_CMD_IMI-#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_MISC-#undef CONFIG_CMD_LOADS---#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */-#define SECTORSIZE 512--#define ADDR_COLUMN 1-#define ADDR_PAGE 2-#define ADDR_COLUMN_PAGE 3--#define NAND_ChipID_UNKNOWN 0x00-#define NAND_MAX_FLOORS 1-#define NAND_MAX_CHIPS 1--#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */-#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */--#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)-#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)--#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))--#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))-/* the following are NOP's in our implementation */-#define NAND_CTL_CLRALE(nandptr)-#define NAND_CTL_SETALE(nandptr)-#define NAND_CTL_CLRCLE(nandptr)-#define NAND_CTL_SETCLE(nandptr) +/* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 #define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */@@ -159,60 +141,35 @@ #define CFG_MEMTEST_START PHYS_SDRAM #define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 +/* PHY */ #define CONFIG_DRIVER_ETHER #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_AT91C_USE_RMII -/* AC Characteristics */-/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */-#define DATAFLASH_TCSS (0xC << 16)-#define DATAFLASH_TCHS (0x1 << 24)--#define CONFIG_HAS_DATAFLASH 1-#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)-#define CFG_MAX_DATAFLASH_BANKS 2-#define CFG_MAX_DATAFLASH_PAGES 16384-#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */-#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */-+/* Nor Flash */ #define PHYS_FLASH_1 0x10000000-#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */+#define PHYS_FLASH_2 0x0 #define CFG_FLASH_BASE PHYS_FLASH_1 #define CFG_MAX_FLASH_BANKS 1-#define CFG_MAX_FLASH_SECT 256+#define CFG_MAX_FLASH_SECT 128+#define PHYS_FLASH_SECT_SIZE (128*1024) #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */+#define CFG_FLASH_UNLOCK_TOUT (2*CFG_HZ) -#undef CFG_ENV_IS_IN_DATAFLASH--#ifdef CFG_ENV_IS_IN_DATAFLASH-#define CFG_ENV_OFFSET 0x20000-#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)-#define CFG_ENV_SIZE 0x2000 /* 0x8000 */-#else+/* Environment Variables location */ #define CFG_ENV_IS_IN_FLASH 1 #ifdef CONFIG_SKIP_LOWLEVEL_INIT #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */ #define CFG_ENV_SIZE 0x10000 /* sectors are 64K here */ #else-#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */-#define CFG_ENV_SIZE 0x2000 /* 0x8000 */+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x7E0000) /* the last sector of flash */+#define CFG_ENV_SIZE 0x20000 /* 128KBytes */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */-#endif /* CFG_ENV_IS_IN_DATAFLASH */- +/* Default Load Address */ #define CFG_LOAD_ADDR 0x21000000 /* default load address */ -#ifdef CONFIG_SKIP_LOWLEVEL_INIT-#define CFG_BOOT_SIZE 0x00 /* 0 KBytes */-#define CFG_U_BOOT_BASE PHYS_FLASH_1-#define CFG_U_BOOT_SIZE 0x60000 /* 384 KBytes */-#else-#define CFG_BOOT_SIZE 0x6000 /* 24 KBytes */-#define CFG_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)-#define CFG_U_BOOT_SIZE 0x10000 /* 64 KBytes */-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */- #define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } #define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */@@ -249,4 +206,4 @@ #error CONFIG_USE_IRQ not supported #endif -#endif+#endif /* __CONFIG_H */diff -urN u-boot-1.3.0.orig/lib_arm/board.c u-boot-1.3.0/lib_arm/board.c--- u-boot-1.3.0.orig/lib_arm/board.c 2007-11-28 11:52:23.000000000 +0800+++ u-boot-1.3.0/lib_arm/board.c 2008-03-18 15:11:55.000000000 +0800@@ -38,6 +38,8 @@ * FIQ Stack: 00ebef7c */ +#define DEBUG+ #include <common.h> #include <command.h> #include <malloc.h>@@ -263,10 +265,28 @@ #ifndef CFG_NO_FLASH ulong size; #endif+#if defined(CONFIG_AT91RM9200DK)+ ulong i;+#endif #if defined(CONFIG_VFD) || defined(CONFIG_LCD) unsigned long addr; #endif +#if defined(CONFIG_AT91RM9200DK)+ i = MEM_READ(0x0); /* back up */+ /* test boot memory */+ MEM_WRITE(0x0, 0x55);+ if (MEM_READ(0x0) != 0x55) {+ /*+ * boot memory is not SRAM+ * so write to 0x01 to MC_RCR in order to realize remap+ */+ MEM_WRITE(0xffffff00, 0x01); /* write 0x01 to MC_RCR */+ } else {+ MEM_WRITE(0x0, i); /* recover */+ }+#endif+ /* Pointer is writable since we allocated a register for it */ gd = (gd_t*)(_armboot_start - CFG_MALLOC_LEN - sizeof(gd_t)); /* compiler optimization barrier needed for GCC >= 3.4 */@@ -290,6 +310,12 @@ display_flash_config (size); #endif /* CFG_NO_FLASH */ +#if defined(CONFIG_AT91RM9200DK) && defined(CONFIG_REMAP_TEST)+ for (i=0; i<0x40; i+=4) {+ printf("0x%08lx: 0x%08lx\n", i, MEM_READ(i));+ }+#endif + #ifdef CONFIG_VFD # ifndef PAGE_SIZE # define PAGE_SIZE 4096⌨️ 快捷键说明
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