📄 int_rom.s
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;/*************************************************************************/
;/* */
;/* Copyright Mentor Graphics Corporation 2002 */
;/* All Rights Reserved. */
;/* */
;/* THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS */
;/* THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS */
;/* SUBJECT TO LICENSE TERMS. */
;/* */
;/*************************************************************************/
;
;/*************************************************************************/
;/* */
;/* FILE NAME VERSION */
;/* */
;/* int_rom.s Nucleus PLUS\ARM PID\ADS 1.13.24 */
;/* */
;/* COMPONENT */
;/* */
;/* IN - Initialization */
;/* */
;/* DESCRIPTION */
;/* */
;/* This file contains the target processor dependent initialization */
;/* routines and data for running from FLASH. */
;/* */
;/* */
;/* FUNCTIONS */
;/* */
;/* INT_Reset Target initialization for */
;/* reset exception */
;/* */
;/* DEPENDENCIES */
;/* */
;/* int_defs.s Initialization constants */
;/* */
;/* HISTORY */
;/* */
;/* NAME DATE REMARKS */
;/* */
;/* D. Driscoll 10 May 2001 Verified and released */
;/* version 1.13.21 */
;/* C. Sheppard 10-15-2001 Released version 1.13.22 */
;/* J. Pregeant 04-17-2002 Released version 1.13.23 */
;/* Jack Pregeant 08-16-2002 Released version 1.13.24 */
;/*************************************************************************/
BIT_SELFREFRESH EQU (1<<22)
;Pre-defined constants
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0
;The location of stacks
UserStack EQU (_STACK_BASEADDRESS-0x3800) ;0x33ff4800 ~
SVCStack EQU (_STACK_BASEADDRESS-0x2800) ;0x33ff5800 ~
UndefStack EQU (_STACK_BASEADDRESS-0x2400) ;0x33ff5c00 ~
AbortStack EQU (_STACK_BASEADDRESS-0x2000) ;0x33ff6000 ~
IRQStack EQU (_STACK_BASEADDRESS-0x1000) ;0x33ff7000 ~
FIQStack EQU (_STACK_BASEADDRESS-0x0) ;0x33ff8000 ~
;Check if tasm.exe(armasm -16 ...@ADS 1.0) is used.
GBLL THUMBCODE
[ {CONFIG} = 16
THUMBCODE SETL {TRUE}
CODE32
|
THUMBCODE SETL {FALSE}
]
MACRO
MOV_PC_LR
[ THUMBCODE
bx lr
|
mov pc,lr
]
MEND
MACRO
MOVEQ_PC_LR
[ THUMBCODE
bxeq lr
|
moveq pc,lr
]
MEND
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;/* NOTE: Define "NU_INT_ROM_SUPPORT" to run out of Flash.
; To do this use the -pd option on the assembler line:
; -pd "NU_INT_ROM_SUPPORT SETL {TRUE}" */
;/*--------------------------------------------------------------*/
IF (:LNOT: :DEF: NU_INT_ROM_SUPPORT)
GBLL NU_INT_ROM_SUPPORT
NU_INT_ROM_SUPPORT SETL {TRUE}
ENDIF
;/*----------------------------------------------------------------*/
IF (:DEF: NU_INT_ROM_SUPPORT)
IF NU_INT_ROM_SUPPORT
;/*************************************************************************/
;/* INCLUDE FILE */
;/*************************************************************************/
;/* Define constants used in low-level initialization. */
GET option.s
GET memcfg.s
GET 2410addr.s
INCLUDE int_defs.s
;/*************************************************************************/
;/* EXTERNAL VARIABLE/FUNCTION DECLARATIONS */
;/*************************************************************************/
IMPORT INT_Undef_Inst
IMPORT INT_Software
IMPORT INT_Prefetch_Abort
IMPORT INT_Data_Abort
IMPORT INT_Reserved
IMPORT INT_IRQ
IMPORT INT_FIQ
;/*************************************************************************/
;/* INTERRUPT TABLES */
;/*************************************************************************/
AREA INT_Init, CODE, READONLY
ENTRY
;/* This is a label used with the ARM linker -first command to place the code
; starting at this label first in the image to be flashed */
EXPORT INT_ROM_ENTRY
INT_ROM_ENTRY
ASSERT :DEF:ENDIAN_CHANGE
[ ENDIAN_CHANGE
ASSERT :DEF:ENTRY_BUS_WIDTH
[ ENTRY_BUS_WIDTH=32
b ChangeBigEndian ;DCD 0xea000007
]
[ ENTRY_BUS_WIDTH=16
andeq r14,r7,r0,lsl #20 ;DCD 0x0007ea00
]
[ ENTRY_BUS_WIDTH=8
streq r0,[r0,-r10,ror #1] ;DCD 0x070000ea
]
|
b INT_Reset
]
LDR pc,Undef_Inst_Addr ; Undefined Instruction
LDR pc,Software_Addr ; Software Generated
LDR pc,Abort_Prefetch_Addr ; Abort Prefetch
LDR pc,Abort_Data_Addr ; Abort Data
LDR pc,Reserved_Addr ; Reserved
LDR pc,IRQ_Addr ; Standard External Interrupt
LDR pc,FIQ_Addr ; Fast External Interrupt
;@0x20
b EnterPWDN
Initialize_Addr DCD INT_Initialize
Undef_Inst_Addr DCD INT_Undef_Inst
Software_Addr DCD INT_Software
Abort_Prefetch_Addr DCD INT_Prefetch_Abort
Abort_Data_Addr DCD INT_Data_Abort
Reserved_Addr DCD INT_Reserved
IRQ_Addr DCD INT_IRQ
FIQ_Addr DCD INT_FIQ
ChangeBigEndian
;@0x24
[ ENTRY_BUS_WIDTH=32
DCD 0xee110f10 ;0xee110f10 => mrc p15,0,r0,c1,c0,0
DCD 0xe3800080 ;0xe3800080 => orr r0,r0,#0x80; //Big-endian
DCD 0xee010f10 ;0xee010f10 => mcr p15,0,r0,c1,c0,0
]
[ ENTRY_BUS_WIDTH=16
DCD 0x0f10ee11
DCD 0x0080e380
DCD 0x0f10ee01
]
[ ENTRY_BUS_WIDTH=8
DCD 0x100f11ee
DCD 0x800080e3
DCD 0x100f01ee
]
DCD 0xffffffff ;swinv 0xffffff is similar with NOP and run well in both endian mode.
DCD 0xffffffff
DCD 0xffffffff
DCD 0xffffffff
DCD 0xffffffff
b INT_Reset
;Function for entering power down mode
; 1. SDRAM should be in self-refresh mode.
; 2. All interrupt should be maksked for SDRAM/DRAM self-refresh.
; 3. LCD controller should be disabled for SDRAM/DRAM self-refresh.
; 4. The I-cache may have to be turned on.
; 5. The location of the following code may have not to be changed.
;void EnterPWDN(int CLKCON);
EnterPWDN
mov r2,r0 ;r2=rCLKCON
tst r0,#0x8 ;POWER_OFF mode?
bne ENTER_POWER_OFF
ENTER_STOP
ldr r0,=REFRESH
ldr r3,[r0] ;r3=rREFRESH
mov r1, r3
orr r1, r1, #BIT_SELFREFRESH
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