port_initial.c

基于C8051F实现数字变压器,用C语言实现其控制思想,液晶,键盘都有.主要的是变压器控制思想.

/*****************************************************************/
/*函数名称： Port_Initial.c                                      */
/*函数功能： 主函数,调用各模块                                   */
/*基本思想:  对所涉及到的端口进行配置                            */
/*修改记录： 无修改记录                                          */
/*编写作者： t483-4-19chenyong                                   */
/*编写日期： 2007-4-14                                           */
/*****************************************************************/

#include "common.h"
#include "delay.h"

void PORT_Init (void)
{
   WDTCN = 0xde;
   WDTCN = 0xad;
  
   SYSCLK_Init();

   SFRPAGE=0x0f;
   XBR1 = 0x04;
   XBR2 = 0x50;                    // Enable crossbar and weak pull-ups
   SFRPAGE=0x0f;
   P0MDOUT	=0x00;
   P1=0xff;
   P1MDOUT |= 0xff;                // enable P1.6 (LED) as push-pull output
   P2MDOUT	=0x00;
   P3MDOUT	=0x00;
   P4MDOUT	=0x00;
   P5MDOUT	=0x00;
   P6MDOUT	=0x00;
   P7MDOUT	=0x00;

}

 
void SYSCLK_Init (void)
{
   int i;                           // delay counter

   char old_SFRPAGE = SFRPAGE;      // Store current SFRPAGE

   SFRPAGE = CONFIG_PAGE;           // set SFR page

   OSCXCN = 0x67;                   // start external oscillator with
                                    // 22.1184MHz crystal

   for (i=0; i < 256; i++) ;        // Wait for osc. to start up

   while (!(OSCXCN & 0x80)) ;       // Wait for crystal osc. to settle

   CLKSEL = 0x01;                   // Select the external osc. as
                                    // the SYSCLK source

   OSCICN = 0x00;                   // Disable the internal osc.

  //Turn on the PLL and increase the system clock by a factor of M/N = 9/4
   SFRPAGE = PLL0_PAGE;

   PLL0CN  = 0x04;                  // Set PLL source as external osc.
   SFRPAGE = LEGACY_PAGE;
   FLSCL   = 0x10;                  // Set FLASH read time for 50MHz clk
                                    // or less
   SFRPAGE = PLL0_PAGE;
   PLL0CN |= 0x01;                  // Enable Power to PLL
   PLL0DIV = 0x03;                  // Set Pre-divide value to N (N = 4)
   PLL0FLT = 0x01;                  // Set the PLL filter register for
                                    // a reference clock from 19 - 30 MHz
                                    // and an output clock from 45 - 80 MHz
   PLL0MUL = 0x0c;                  // Multiply SYSCLK by M (M = 9)

   for (i=0; i < 256; i++) ;        // Wait at least 5us
   PLL0CN  |= 0x02;                 // Enable the PLL
   while(!(PLL0CN & 0x10));         // Wait until PLL frequency is locked
   CLKSEL  = 0x02;                  // Select PLL as SYSCLK source	    

   SFRPAGE = old_SFRPAGE;           // restore SFRPAGE
}