port_initial.c

基于8051F实现数字电压表功能.用液晶作为显示界面,精度很高.

/*****************************************************************/
/*函数名称： Port_Initial.c                                      */
/*函数功能： 主函数,调用各模块                                   */
/*基本思想:  对所涉及到的端口进行配置                            */
/*修改记录： 无修改记录                                          */
/*编写作者： t483-4-19chenyong                                   */
/*编写日期： 2007-4-14                                           */
/*****************************************************************/

#include "common.h"
//#include "window.h" 
#include "delay.h"

void Port_Initial()
{
//看门狗禁止
	WDTCN = 0x07;	
    WDTCN = 0xDE;   
   	WDTCN = 0xAD;
//	SYSCLK_Init();
//交叉开关配置T2EX=P0.0
    SFRPAGE = 0x0f;
	XBR0 = 0x00;	
	XBR1 = 0x00;	
	XBR2 = 0x40;  
//管脚输出配置，P0口为开漏输出，其中P0.0接上拉电阻，P0为数字输入口
    SFRPAGE = 0x0f;
 	P0MDOUT = 0x00; 
	P1MDOUT = 0x00; 
 	P1MDIN  = 0x00;
/*	  
//晶振配置，采用内部晶振8分频 
    SFRPAGE=0x0f;
    OSCXCN =  0x00;	
    OSCICN =  0x84;	
                    //采用内部晶振，为24.5MHZ8分频
  */
}



 
void SYSCLK_Init (void)
{
   int i;                           // delay counter

   char old_SFRPAGE = SFRPAGE;      // Store current SFRPAGE

   SFRPAGE = CONFIG_PAGE;           // set SFR page

   OSCXCN = 0x67;                   // start external oscillator with
                                    // 22.1184MHz crystal

   for (i=0; i < 256; i++) ;        // Wait for osc. to start up

   while (!(OSCXCN & 0x80)) ;       // Wait for crystal osc. to settle

   CLKSEL = 0x01;                   // Select the external osc. as
                                    // the SYSCLK source

   OSCICN = 0x00;                   // Disable the internal osc.

  //Turn on the PLL and increase the system clock by a factor of M/N = 9/4
   SFRPAGE = PLL0_PAGE;

   PLL0CN  = 0x04;                  // Set PLL source as external osc.
   SFRPAGE = LEGACY_PAGE;
   FLSCL   = 0x10;                  // Set FLASH read time for 50MHz clk
                                    // or less
   SFRPAGE = PLL0_PAGE;
   PLL0CN|=0x01;                  // Enable Power to PLL
   PLL0DIV = 0x03;                  // Set Pre-divide value to N (N = 4)
   PLL0FLT = 0x01;                  // Set the PLL filter register for
                                    // a reference clock from 19 - 30 MHz
                                    // and an output clock from 45 - 80 MHz
   PLL0MUL = 0x0c;                  // Multiply SYSCLK by M (M = 9)

   for (i=0; i < 256; i++) ;        // Wait at least 5us
   PLL0CN|=0x02;                 // Enable the PLL
   while(!(PLL0CN & 0x10));         // Wait until PLL frequency is locked
   CLKSEL  = 0x02;                  // Select PLL as SYSCLK source	    

   SFRPAGE = old_SFRPAGE;           // restore SFRPAGE
}