port_initial.lst

基于8051F实现数字电压表功能.用液晶作为显示界面,精度很高.

C51 COMPILER V8.02   PORT_INITIAL                                                          03/29/2008 22:13:16 PAGE 1   


C51 COMPILER V8.02, COMPILATION OF MODULE PORT_INITIAL
OBJECT MODULE PLACED IN Port_Initial.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE Port_Initial.c BROWSE DEBUG OBJECTEXTEND

line level    source

   1          /*****************************************************************/
   2          /*函数名称： Port_Initial.c                                      */
   3          /*函数功能： 主函数,调用各模块                                   */
   4          /*基本思想:  对所涉及到的端口进行配置                            */
   5          /*修改记录： 无修改记录                                          */
   6          /*编写作者： t483-4-19chenyong                                   */
   7          /*编写日期： 2007-4-14                                           */
   8          /*****************************************************************/
   9          
  10          #include "common.h"
  11          //#include "window.h" 
  12          #include "delay.h"
  13          
  14          void Port_Initial()
  15          {
  16   1      //看门狗禁止
  17   1              WDTCN = 0x07;   
  18   1          WDTCN = 0xDE;   
  19   1              WDTCN = 0xAD;
  20   1      //      SYSCLK_Init();
  21   1      //交叉开关配置T2EX=P0.0
  22   1          SFRPAGE = 0x0f;
  23   1              XBR0 = 0x00;    
  24   1              XBR1 = 0x00;    
  25   1              XBR2 = 0x40;  
  26   1      //管脚输出配置，P0口为开漏输出，其中P0.0接上拉电阻，P0为数字输入口
  27   1          SFRPAGE = 0x0f;
  28   1              P0MDOUT = 0x00; 
  29   1              P1MDOUT = 0x00; 
  30   1              P1MDIN  = 0x00;
  31   1      /*        
  32   1      //晶振配置，采用内部晶振8分频 
  33   1          SFRPAGE=0x0f;
  34   1          OSCXCN =  0x00;     
  35   1          OSCICN =  0x84;     
  36   1                          //采用内部晶振，为24.5MHZ8分频
  37   1        */
  38   1      }
  39          
  40          
  41          
  42           
  43          void SYSCLK_Init (void)
  44          {
  45   1         int i;                           // delay counter
  46   1      
  47   1         char old_SFRPAGE = SFRPAGE;      // Store current SFRPAGE
  48   1      
  49   1         SFRPAGE = CONFIG_PAGE;           // set SFR page
  50   1      
  51   1         OSCXCN = 0x67;                   // start external oscillator with
  52   1                                          // 22.1184MHz crystal
  53   1      
  54   1         for (i=0; i < 256; i++) ;        // Wait for osc. to start up
  55   1      
C51 COMPILER V8.02   PORT_INITIAL                                                          03/29/2008 22:13:16 PAGE 2   

  56   1         while (!(OSCXCN & 0x80)) ;       // Wait for crystal osc. to settle
  57   1      
  58   1         CLKSEL = 0x01;                   // Select the external osc. as
  59   1                                          // the SYSCLK source
  60   1      
  61   1         OSCICN = 0x00;                   // Disable the internal osc.
  62   1      
  63   1        //Turn on the PLL and increase the system clock by a factor of M/N = 9/4
  64   1         SFRPAGE = PLL0_PAGE;
  65   1      
  66   1         PLL0CN  = 0x04;                  // Set PLL source as external osc.
  67   1         SFRPAGE = LEGACY_PAGE;
  68   1         FLSCL   = 0x10;                  // Set FLASH read time for 50MHz clk
  69   1                                          // or less
  70   1         SFRPAGE = PLL0_PAGE;
  71   1         PLL0CN|=0x01;                  // Enable Power to PLL
  72   1         PLL0DIV = 0x03;                  // Set Pre-divide value to N (N = 4)
  73   1         PLL0FLT = 0x01;                  // Set the PLL filter register for
  74   1                                          // a reference clock from 19 - 30 MHz
  75   1                                          // and an output clock from 45 - 80 MHz
  76   1         PLL0MUL = 0x0c;                  // Multiply SYSCLK by M (M = 9)
  77   1      
  78   1         for (i=0; i < 256; i++) ;        // Wait at least 5us
  79   1         PLL0CN|=0x02;                 // Enable the PLL
  80   1         while(!(PLL0CN & 0x10));         // Wait until PLL frequency is locked
  81   1         CLKSEL  = 0x02;                  // Select PLL as SYSCLK source          
  82   1      
  83   1         SFRPAGE = old_SFRPAGE;           // restore SFRPAGE
  84   1      } 
  85          
  86            


MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =    120    ----
   CONSTANT SIZE    =   ----    ----
   XDATA SIZE       =   ----    ----
   PDATA SIZE       =   ----    ----
   DATA SIZE        =   ----    ----
   IDATA SIZE       =   ----    ----
   BIT SIZE         =   ----    ----
END OF MODULE INFORMATION.


C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)