port_init.lst

基于8051F单片机,实现1024点的FFT 用C 语言实现的.效果与FPGA实现相同.

C51 COMPILER V8.02   PORT_INIT                                                             05/09/2008 21:51:22 PAGE 1   


C51 COMPILER V8.02, COMPILATION OF MODULE PORT_INIT
OBJECT MODULE PLACED IN PORT_Init.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE PORT_Init.c BROWSE DEBUG OBJECTEXTEND

line level    source

   1          
   2          #include <c8051f120.h>                 // SFR declarations
   3          #include <stdio.h>
   4          
   5          //-----------------------------------------------------------------------------
   6          // Initialization Routines
   7          //-----------------------------------------------------------------------------
   8          
   9          //-----------------------------------------------------------------------------
  10          // PORT_Init
  11          //-----------------------------------------------------------------------------
  12          //
  13          // Configure the Crossbar and GPIO ports
  14          //
  15          void PORT_Init (void)
  16          {
  17   1       char old_SFRPAGE = SFRPAGE;         // Store current SFRPAGE
  18   1       SFRPAGE = CONFIG_PAGE;           // Switch to configuration page
  19   1      
  20   1      
  21   1         XBR0    = 0x04;                  // Enable UART0 on crossbar
  22   1         XBR1    = 0x00;
  23   1         XBR2    = 0x40;                  // Enable crossbar and weak pull-ups
  24   1         P0MDOUT |= 0x01;                 // Set TX0 pin to push-pull
  25   1      
  26   1         SFRPAGE = old_SFRPAGE;           // restore SFRPAGE
  27   1      }
  28          
  29          //-----------------------------------------------------------------------------
  30          // SYSCLK_Init
  31          //-----------------------------------------------------------------------------
  32          //
  33          // This routine initializes the system clock to use an external 22.1184 MHz
  34          // crystal oscillator multiplied by a factor of 9/4 using the PLL as its
  35          // clock source. The resulting frequency is 22.1184 MHz * 9/4 = 49.7664 MHz
  36          //
  37          void SYSCLK_Init (void)
  38          {
  39   1         int i;                           // delay counter
  40   1      
  41   1         char old_SFRPAGE = SFRPAGE;      // Store current SFRPAGE
  42   1      
  43   1         SFRPAGE = CONFIG_PAGE;           // set SFR page
  44   1      
  45   1         OSCXCN = 0x67;                   // start external oscillator with
  46   1                                          // 22.1184MHz crystal
  47   1      
  48   1         for (i=0; i < 256; i++) ;        // Wait for osc. to start up
  49   1      
  50   1         while (!(OSCXCN & 0x80)) ;       // Wait for crystal osc. to settle
  51   1      
  52   1         CLKSEL = 0x01;                   // Select the external osc. as
  53   1                                          // the SYSCLK source
  54   1      
  55   1         OSCICN = 0x00;                   // Disable the internal osc.
C51 COMPILER V8.02   PORT_INIT                                                             05/09/2008 21:51:22 PAGE 2   

  56   1      
  57   1         //Turn on the PLL and increase the system clock by a factor of M/N = 9/4
  58   1         SFRPAGE = PLL0_PAGE;
  59   1      
  60   1         PLL0CN  = 0x04;                  // Set PLL source as external osc.
  61   1         SFRPAGE = LEGACY_PAGE;
  62   1         FLSCL   = 0x10;                  // Set FLASH read time for 50MHz clk
  63   1                                          // or less
  64   1         SFRPAGE = PLL0_PAGE;
  65   1         PLL0CN |= 0x01;                  // Enable Power to PLL
  66   1         PLL0DIV = 0x04;                  // Set Pre-divide value to N (N = 4)
  67   1         PLL0FLT = 0x01;                  // Set the PLL filter register for
  68   1                                          // a reference clock from 19 - 30 MHz
  69   1                                          // and an output clock from 45 - 80 MHz
  70   1         PLL0MUL = 0x09;                  // Multiply SYSCLK by M (M = 9)
  71   1      
  72   1         for (i=0; i < 256; i++) ;        // Wait at least 5us
  73   1         PLL0CN  |= 0x02;                 // Enable the PLL
  74   1         while(!(PLL0CN & 0x10));         // Wait until PLL frequency is locked
  75   1         CLKSEL  = 0x02;                  // Select PLL as SYSCLK source
  76   1      
  77   1         SFRPAGE = old_SFRPAGE;           // restore SFRPAGE
  78   1      }


MODULE INFORMATION:   STATIC OVERLAYABLE
   CODE SIZE        =    110    ----
   CONSTANT SIZE    =   ----    ----
   XDATA SIZE       =   ----    ----
   PDATA SIZE       =   ----    ----
   DATA SIZE        =   ----    ----
   IDATA SIZE       =   ----    ----
   BIT SIZE         =   ----    ----
END OF MODULE INFORMATION.


C51 COMPILATION COMPLETE.  0 WARNING(S),  0 ERROR(S)