init_core_s.s

yamon2.27.tar.gz bootloader 在au1200上完全通过

/************************************************************************
 *
 *  init_core_s.S
 *
 *  Core card specific startup code (assembler)
 *
 *
 * ######################################################################
 *
 * Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved. 
 * 
 * Unpublished rights reserved under the Copyright Laws of the United States of 
 * America. 
 * 
 * This document contains information that is proprietary to MIPS Technologies, 
 * Inc. ("MIPS Technologies"). Any copying, modifying or use of this information 
 * (in whole or in part) which is not expressly permitted in writing by MIPS 
 * Technologies or a contractually-authorized third party is strictly 
 * prohibited. At a minimum, this information is protected under unfair 
 * competition laws and the expression of the information contained herein is 
 * protected under federal copyright laws. Violations thereof may result in 
 * criminal penalties and fines. 
 * MIPS Technologies or any contractually-authorized third party reserves the 
 * right to change the information contained in this document to improve 
 * function, design or otherwise. MIPS Technologies does not assume any 
 * liability arising out of the application or use of this information. Any 
 * license under patent rights or any other intellectual property rights owned 
 * by MIPS Technologies or third parties shall be conveyed by MIPS Technologies 
 * or any contractually-authorized third party in a separate license agreement 
 * between the parties. 
 * The information contained in this document constitutes one or more of the 
 * following: commercial computer software, commercial computer software 
 * documentation or other commercial items. If the user of this information, or 
 * any related documentation of any kind, including related technical data or 
 * manuals, is an agency, department, or other entity of the United States 
 * government ("Government"), the use, duplication, reproduction, release, 
 * modification, disclosure, or transfer of this information, or any related 
 * documentation of any kind, is restricted in accordance with Federal 
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal 
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use of 
 * this information by the Government is further restricted in accordance with 
 * the terms of the license agreement(s) and/or applicable contract terms and 
 * conditions covering this information from MIPS Technologies or any 
 * contractually-authorized third party. 
 *
 ************************************************************************/

/************************************************************************
 *  Include files
 ************************************************************************/
	
#include <sysdefs.h>
#include <mips.h>
#include <init.h>
#include <product.h>
#include <gt64120.h>

/************************************************************************
 *  Definitions
 ************************************************************************/

#define FUNC_INIT		0
#define FUNC_GET_PCIMEM_BASE	1
#define FUNC_GET_MAX_SDRAM_BANK	2
#define FUNC_CONFIG_WRITE	3
#define FUNC_CONFIG_READ	4
#define FUNC_CONFIGURE_SDRAM	5
#define FUNC_SETUP_DECODE	6
#define FUNC_REMAP_PCI_IO	7
	
/************************************************************************
 *  Public variables
 ************************************************************************/

/************************************************************************
 *  Static variables
 ************************************************************************/

/************************************************************************
 *  Implementation : Public functions
 ************************************************************************/

		
	.set noreorder


/************************************************************************	
 *
 *                          sys_core_init
 *  Description :
 *  -------------
 *
 *  Initialise North bridge just enough so that we can access PCI.
 *
 *  Parameters :
 *  ------------
 *
 *  a0 = Base address to be used for access to North Bridge registers.
 *	
 *  Return values :
 *  ---------------
 *
 *  v0 = error code (0 = OK)
 *  v1 = 1 -> Request software reset
 *
 *  None
 *
 ************************************************************************/
LEAF(sys_core_init)

	b	access_core
	li	t9, FUNC_INIT
	
END(sys_core_init)	


/************************************************************************	
 *
 *                          sys_core_get_pcimem_base
 *  Description :
 *  -------------
 *
 *  Return base address for PCI memory cycles.
 *
 *  Parameters :
 *  ------------
 * 
 *  None
 *
 *  Return values :
 *  ---------------
 *
 *  v0 = Base address for PCI memory cycles
 *
 ************************************************************************/
LEAF(sys_core_get_pcimem_base)

	b	access_core
	li	t9, FUNC_GET_PCIMEM_BASE
	
END(sys_core_get_pcimem_base)	


/************************************************************************	
 *
 *                          sys_core_get_max_sdram_bank
 *  Description :
 *  -------------
 *
 *  Return max SDRAM module bank size
 *
 *  Parameters :
 *  ------------
 * 
 *  None
 *
 *  Return values :
 *  ---------------
 *
 *  v0 = Max SDRAM module bank size
 *
 ************************************************************************/
LEAF(sys_core_get_max_sdram_bank)

	b	access_core
	li	t9, FUNC_GET_MAX_SDRAM_BANK
		
END(sys_core_get_max_sdram_bank)	


/************************************************************************	
 *
 *                          sys_core_config_write
 *  Description :
 *  -------------
 *
 *  Perform 32 bit PCI configuration write cycle on local bus.
 *
 *  Parameters :
 *  ------------
 * 
 *  a0 = device number (function 0 assumed)
 *  a1 = register
 *  a2 = data
 *  a3 = base address of controller
 *
 *  Return values :
 *  ---------------
 *
 *  v0 = 0 if OK
 *  v0 = ERROR_NB_CONFIG if not OK
 *
 ************************************************************************/
LEAF(sys_core_config_write)

	b	access_core
	li	t9, FUNC_CONFIG_WRITE
		
END(sys_core_config_write)	
	

/************************************************************************	
 *
 *                          sys_core_config_read
 *  Description :
 *  -------------
 *
 *  Perform 32 bit PCI configuration read cycle on local bus.
 *
 *  Parameters :
 *  ------------
 * 
 *  a0 = device number (function 0 assumed)
 *  a1 = register
 *  a2 = base address of controller
 *
 *  Return values :
 *  ---------------
 *
 *  v0 = 0 if OK
 *  v0 = ERROR_NB_CONFIG if not OK
 *  v1 = data read (if OK)
 *
 ************************************************************************/
LEAF(sys_core_config_read)

	b	access_core
	li	t9, FUNC_CONFIG_READ
	
END(sys_core_config_read)	


/************************************************************************	
 *
 *                          sys_core_configure_sdram
 *  Description :
 *  -------------
 *
 *  Setup North bridge SDRAM configuration
 *
 *  Parameters :
 *  ------------
 * 
 *  a0 = Worst case (lowest) bus freq. (MHz) for setting timing parms.
 *  a1 = SDRAM device size (in Mbit)
 *  a2 = SDRAM device bank count (not the module bank count)
 *  a3 = Module bank 0 size
 *  t0 = Module bank 1 size
 *  t1 = base address of controller
 *	
 *  Return values :
 *  ---------------
 *
 *  0 :				No error.
 *  ERROR_SDRAM_CASLAT :	Module does not support CAS latency = 2.
 *  ERROR_SDRAM_BURSTLEN :	Module does not support burslength = 8.
 *  ERROR_SDRAM_ERRORCHECK :	Module requires ECC error check.
 *  ERROR_SDRAM_DEV_BANKS :	SDRAM devices have bank counts other 
 *				than than 2/4.
 *
 ************************************************************************/
LEAF(sys_core_configure_sdram)

	b	access_core
	li	t9, FUNC_CONFIGURE_SDRAM
	
END(sys_core_configure_sdram)	

		
/************************************************************************	
 *
 *                          sys_core_setup_decode
 *  Description :
 *  -------------
 *
 *  Setup North Bridge memory decoding (except for SDRAM).
 *
 *  Parameters :
 *  ------------
 *
 *  a0 = PCI memory space base
 *  a1 = PCI memory space size
 *  a2 = PCI I/O space base
 *  a3 = PCI I/O space size
 *  t0 = CBUS base
 *  t1 = CBUS size
 *  t2 = base address of controller
 *
 *  Return values :
 *  ---------------
 *
 *  0 :				No error.
 *  ERROR_NB_DECODE :		Illegal ranges requested.
 *
 ************************************************************************/
LEAF(sys_core_setup_decode)

	b	access_core
	li	t9, FUNC_SETUP_DECODE
	
END(sys_core_setup_decode)	


/************************************************************************	
 *
 *                          sys_core_remap_pci_io
 *  Description :
 *  -------------
 *
 *  Remap PCI IO range so that PCI IO range starts at address 0 on
 *  PCI (North Bridge no longer transparent for PCI IO).
 *
 *  Parameters :
 *  ------------
 *
 *  a0 = base address of controller
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
LEAF(sys_core_remap_pci_io)

	b	access_core
	li	t9, FUNC_REMAP_PCI_IO
	
END(sys_core_remap_pci_io)	
	
	
/************************************************************************
 *  Implementation : Static functions
 ************************************************************************/

	
/************************************************************************	
 *		access_core
 ************************************************************************/		
SLEAF(access_core)

	/* Determine core board */
	li	t7, MIPS_REVISION
	li	t8, MIPS_REVISION_CORID_MSK
	and	t7, t8
	li	t8, MIPS_REVISION_CORID_SHF
	srlv	t7, t7, t8

	li	t8, MIPS_REVISION_CORID_QED_RM5261
	beq	t7, t8, access_gt64120
	nop
	li	t8, MIPS_REVISION_CORID_CORE_LV
	beq	t7, t8, access_gt64120
	nop

	/* Add new core cards here ! */

	/* Unknown core card */
	jr	ra
	li	v0, ERROR_CORE_UNKNOWN

access_gt64120:	
	
	/* GT64120 */

        li      t8, FUNC_INIT
	bne     t9, t8, 1f
	nop
	j	gt64120_init
	nop
1:	
        li      t8, FUNC_GET_PCIMEM_BASE
	bne     t9, t8, 1f
	nop
	j	gt64120_get_pcimem_base
	nop
1:	
        li      t8, FUNC_GET_MAX_SDRAM_BANK
	bne     t9, t8, 1f
	nop
	j	gt64120_get_max_sdram_bank
	nop
1:	
        li      t8, FUNC_CONFIG_WRITE
	bne     t9, t8, 1f
	nop
	j	gt64120_config_write
	nop
1:	
        li      t8, FUNC_CONFIG_READ
	bne     t9, t8, 1f
	nop
	j	gt64120_config_read
	nop
1:	
        li      t8, FUNC_CONFIGURE_SDRAM
	bne     t9, t8, 1f
	nop
	j	gt64120_configure_sdram
	nop
1:	
        li      t8, FUNC_SETUP_DECODE
	bne     t9, t8, 1f
	nop
	j	gt64120_setup_decode
	nop
1:	
        /* FUNC_REMAP_PCI_IO */
	j	gt64120_remap_pci_io
	nop
	
END(access_core)