📄 cache.s
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#define config1 t9
/*
* I-cache associativity
*/
li t8, C0_CONFIG1_IA_MSK
and t8, config1
li t7, C0_CONFIG1_IA_SHF
srl t8, t7
addiu v0,t8,1 /* t8 = associativity */
jr ra
nop
icache_assoc_qed_rm5261:
li v0, QED_RM5261_ICACHE_ASSOC
jr ra
nop
END(sys_determine_icache_assoc_flash)
/************************************************************************
*
* sys_determine_dcache_linesize_flash
* Description :
* -------------
*
* Determine DCACHE linesize
*
* input : a0 = processor ID
*
* Return values :
* ---------------
*
* v0 = DCACHE linesize in bytes
*
************************************************************************/
LEAF(sys_determine_dcache_linesize_flash)
/* Check if it is a MIPS32/64 processor */
li t9, C0_PRID_COMP_MSK
and t9, a0
srl t9, C0_PRID_COMP_SHF
li t8, C0_PRID_COMP_NOT_MIPS32_64
bne t9, t8, dcache_linesize_mips32
nop
/* Not a MIPS32/64 processor */
li t9, QED_RM52XX
beq a0, t9, dcache_linesize_qed_rm5261
nop
/* Unknown CPU */
dcache_linesize_zero:
jr ra
move v0, zero
dcache_linesize_mips32:
/* Read CONFIG1 register, which holds implementation data
/* t9 = $25, CONFIG1 = $16
*/
MFC0_SEL_OPCODE( 25, 16, C0_CONFIG1_SEL )
#define config1 t9
/* D-cache line size */
li t8, C0_CONFIG1_DL_MSK
and t8, config1
beq t8, zero, dcache_linesize_zero
li t7, C0_CONFIG1_DL_SHF
srl t8, t7
li t7, 0x2
sll v0, t7, t8
jr ra
nop
dcache_linesize_qed_rm5261:
li v0, QED_RM5261_DCACHE_LSIZE
jr ra
nop
END(sys_determine_dcache_linesize_flash)
/************************************************************************
*
* sys_determine_dcache_lines_flash
* Description :
* -------------
*
* Determine number of DCACHE lines
*
* input : a0 = processor ID
*
* Return values :
* ---------------
*
* v0 = number of DCACHE lines
*
************************************************************************/
LEAF(sys_determine_dcache_lines_flash)
/* Check if it is a MIPS32/64 processor */
li t9, C0_PRID_COMP_MSK
and t9, a0
srl t9, C0_PRID_COMP_SHF
li t8, C0_PRID_COMP_NOT_MIPS32_64
bne t9, t8, dcache_lines_mips32
nop
/* Not a MIPS32/64 processor */
li t9, QED_RM52XX
beq a0, t9, dcache_lines_qed_rm5261
nop
/* Unknown CPU */
dcache_lines_zero:
jr ra
move v0, zero
dcache_lines_mips32:
/* Read CONFIG1 register, which holds implementation data
/* t9 = $25, CONFIG1 = $16
*/
MFC0_SEL_OPCODE( 25, 16, C0_CONFIG1_SEL )
#define config1 t9
/*
* D-cache lines
* Calculated as associativity * sets per way
*/
li t8, C0_CONFIG1_DA_MSK
and t8, config1
li t7, C0_CONFIG1_DA_SHF
srl t8, t7
addiu t8,1 /* t8 = associativity */
li t7, C0_CONFIG1_DS_MSK
and t7, config1
li t9, C0_CONFIG1_DS_SHF
srl t7, t9
li t9, 0x40
sll t7, t9, t7 /* t7 = sets per way */
multu t8, t7
MFLO( v0 )
jr ra
nop
dcache_lines_qed_rm5261:
li v0, (QED_RM5261_DCACHE_SIZE / QED_RM5261_DCACHE_LSIZE)
jr ra
nop
END(sys_determine_dcache_lines_flash)
/************************************************************************
*
* sys_determine_dcache_assoc_flash
* Description :
* -------------
*
* Determine DCACHE associativity
*
* input : a0 = processor ID
*
* Return values :
* ---------------
*
* v0 = DCACHE associativity
*
************************************************************************/
LEAF(sys_determine_dcache_assoc_flash)
/* Check if it is a MIPS32/64 processor */
li t9, C0_PRID_COMP_MSK
and t9, a0
srl t9, C0_PRID_COMP_SHF
li t8, C0_PRID_COMP_NOT_MIPS32_64
bne t9, t8, dcache_assoc_mips32
nop
/* Not a MIPS32/64 processor */
li t9, QED_RM52XX
beq a0, t9, dcache_assoc_qed_rm5261
nop
/* Unknown CPU */
dcache_assoc_zero:
jr ra
move v0, zero
dcache_assoc_mips32:
/* Read CONFIG1 register, which holds implementation data
/* t9 = $25, CONFIG1 = $16
*/
MFC0_SEL_OPCODE( 25, 16, C0_CONFIG1_SEL )
#define config1 t9
/*
* I-cache associativity
*/
li t8, C0_CONFIG1_DA_MSK
and t8, config1
li t7, C0_CONFIG1_DA_SHF
srl t8, t7
addiu v0,t8,1 /* t8 = associativity */
jr ra
nop
dcache_assoc_qed_rm5261:
li v0, QED_RM5261_DCACHE_ASSOC
jr ra
nop
END(sys_determine_dcache_assoc_flash)
/************************************************************************
*
* sys_init_icache
* Description :
* -------------
*
* Invalidate entire ICACHE
*
* input : a0 = cache size (bytes)
* a1 = line size (bytes)
*
* Return values :
* ---------------
*
* None
*
************************************************************************/
LEAF( sys_init_icache )
/* a0 = cache size
* a1 = line size
*/
MTC0( zero, C0_TAGLO )
MTC0( zero, C0_TAGHI ) /* TagHi is not really used */
/* Calc an address that will correspond to the first cache line */
li a2, KSEG0BASE
/* Calc an address that will correspond to the last cache line */
addu a3, a2, a0
subu a3, a1
/* Loop through all lines, invalidating each of them */
1:
.set mips3
cache ICACHE_INDEX_STORE_TAG, 0(a2) /* clear tag */
.set mips0
bne a2, a3, 1b
addu a2, a1
jr ra
nop
END( sys_init_icache )
/************************************************************************
*
* sys_init_dcache
* Description :
* -------------
*
* Invalidate entire ICACHE
*
* input : a0 = cache size (bytes)
* a1 = line size (bytes)
*
* Return values :
* ---------------
*
* None
*
************************************************************************/
LEAF( sys_init_dcache )
/* a0 = cache size
* a1 = line size
*/
MTC0( zero, C0_TAGLO )
MTC0( zero, C0_TAGHI ) /* TagHi is not really used */
/* Calc an address that will correspond to the first cache line */
li a2, KSEG0BASE
/* Calc an address that will correspond to the last cache line */
addu a3, a2, a0
subu a3, a1
/* Loop through all lines, invalidating each of them */
1:
.set mips3
cache DCACHE_INDEX_STORE_TAG, 0(a2) /* clear tag */
.set mips0
bne a2, a3, 1b
addu a2, a1
jr ra
nop
END( sys_init_dcache )
/************************************************************************
* Implementation : Static functions
************************************************************************/
/* Messages */
.text
MSG( msg_cache, "CACHE" )
MSG( msg_init_icache, "ICACHE" )
MSG( msg_init_dcache, "DCACHE" )
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