cache.s

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/************************************************************************
 *
 *  cache.S
 *
 *  Cache functions
 *
 *
 * ######################################################################
 *
 * Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved. 
 * 
 * Unpublished rights reserved under the Copyright Laws of the United States of 
 * America. 
 * 
 * This document contains information that is proprietary to MIPS Technologies, 
 * Inc. ("MIPS Technologies"). Any copying, modifying or use of this information 
 * (in whole or in part) which is not expressly permitted in writing by MIPS 
 * Technologies or a contractually-authorized third party is strictly 
 * prohibited. At a minimum, this information is protected under unfair 
 * competition laws and the expression of the information contained herein is 
 * protected under federal copyright laws. Violations thereof may result in 
 * criminal penalties and fines. 
 * MIPS Technologies or any contractually-authorized third party reserves the 
 * right to change the information contained in this document to improve 
 * function, design or otherwise. MIPS Technologies does not assume any 
 * liability arising out of the application or use of this information. Any 
 * license under patent rights or any other intellectual property rights owned 
 * by MIPS Technologies or third parties shall be conveyed by MIPS Technologies 
 * or any contractually-authorized third party in a separate license agreement 
 * between the parties. 
 * The information contained in this document constitutes one or more of the 
 * following: commercial computer software, commercial computer software 
 * documentation or other commercial items. If the user of this information, or 
 * any related documentation of any kind, including related technical data or 
 * manuals, is an agency, department, or other entity of the United States 
 * government ("Government"), the use, duplication, reproduction, release, 
 * modification, disclosure, or transfer of this information, or any related 
 * documentation of any kind, is restricted in accordance with Federal 
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal 
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use of 
 * this information by the Government is further restricted in accordance with 
 * the terms of the license agreement(s) and/or applicable contract terms and 
 * conditions covering this information from MIPS Technologies or any 
 * contractually-authorized third party. 
 *
 ************************************************************************/


/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <mips.h>
#include <init.h>
		
/************************************************************************
 *  Definitions
 ************************************************************************/

/************************************************************************
 *  Public variables
 ************************************************************************/

/************************************************************************
 *  Static variables
 ************************************************************************/

/************************************************************************
 *  Implementation : Public functions
 ************************************************************************/

	.set noreorder
	
/************************************************************************
 *
 *                          sys_init_cache
 *  Description :
 *  -------------
 *
 *  Invalidate I and D caches
 *
 *  input : k1 = processor ID
 *	
 *  Return values :
 *  ---------------
 *
 *  Always 0
 *
 ************************************************************************/
LEAF(sys_init_cache)

	/**** Determine cache settings ****/

	/* This code was linked cached, but is running uncached since
	 * caches have not been initialised yet.
	 */
	
#define RA			t4
#define icache_size		t3
#define icache_linesize		t2
#define dcache_size		t1
#define dcache_linesize		t0

	DISP_STR( msg_cache )
	
	move	RA, ra

	move	a0, k1
	
	bal	sys_determine_icache_linesize_flash
	nop
	move	icache_linesize, v0

	bal	sys_determine_icache_lines_flash
	nop
	multu	icache_linesize, v0
	MFLO(	icache_size)

	bal	sys_determine_dcache_linesize_flash
	nop
	move	dcache_linesize, v0

	bal	sys_determine_dcache_lines_flash
	nop
	multu	dcache_linesize, v0
	MFLO(	dcache_size)


	/* Initialise instruction cache */
	DISP_STR( msg_init_icache )
	move	a0, icache_size
	move	a1, icache_linesize
	bal	sys_init_icache
	nop
	
	/* Initialise data cache */
	DISP_STR( msg_init_dcache )
	move	a0, dcache_size
	move	a1, dcache_linesize
	bal	sys_init_dcache
	nop

	/* Done */

	jr	RA
	move	v0, zero

END(sys_init_cache)



/************************************************************************
 *
 *                          sys_determine_icache_linesize_flash
 *  Description :
 *  -------------
 *
 *  Determine ICACHE linesize
 *
 *  input : a0 = processor ID
 *	
 *  Return values :
 *  ---------------
 *
 *  v0 = ICACHE linesize in bytes
 *
 ************************************************************************/
LEAF(sys_determine_icache_linesize_flash)	

	/* Check if it is a MIPS32/64 processor */	
	li      t9, C0_PRID_COMP_MSK
	and	t9, a0
	srl	t9, C0_PRID_COMP_SHF
	li	t8, C0_PRID_COMP_NOT_MIPS32_64
	bne	t9, t8, icache_linesize_mips32
	nop
	/* Not a MIPS32/64 processor */
	li	t9, QED_RM52XX
	beq	a0, t9, icache_linesize_qed_rm5261
	nop
	/* Unknown CPU */
icache_linesize_zero:
	jr	ra
	move	v0, zero

icache_linesize_mips32:
	
	/* Read CONFIG1 register, which holds implementation data
	/* t9 = $25, CONFIG1 = $16 
	 */
	
	MFC0_SEL_OPCODE( 25, 16, C0_CONFIG1_SEL )     

#define config1	t9

	/* I-cache line size */
	li	t8, C0_CONFIG1_IL_MSK
	and	t8, config1
	beq	t8, zero, icache_linesize_zero
	li	t7, C0_CONFIG1_IL_SHF
	srl	t8, t7
	li	t7, 0x2
	sll	v0, t7, t8

	jr	ra
	nop

icache_linesize_qed_rm5261:
	li	v0, QED_RM5261_ICACHE_LSIZE
	jr	ra
	nop

END(sys_determine_icache_linesize_flash)	
	


/************************************************************************
 *
 *                          sys_determine_icache_lines_flash
 *  Description :
 *  -------------
 *
 *  Determine number of ICACHE lines
 *
 *  input : a0 = processor ID
 *	
 *  Return values :
 *  ---------------
 *
 *  v0 = number of ICACHE lines
 *
 ************************************************************************/
LEAF(sys_determine_icache_lines_flash)	

	/* Check if it is a MIPS32/64 processor */	
	li      t9, C0_PRID_COMP_MSK
	and	t9, a0
	srl	t9, C0_PRID_COMP_SHF
	li	t8, C0_PRID_COMP_NOT_MIPS32_64
	bne	t9, t8, icache_lines_mips32
	nop
	/* Not a MIPS32/64 processor */
	li	t9, QED_RM52XX
	beq	a0, t9, icache_lines_qed_rm5261
	nop
	/* Unknown CPU */
icache_lines_zero:
	jr	ra
	move	v0, zero

icache_lines_mips32:
	
	/* Read CONFIG1 register, which holds implementation data
	/* t9 = $25, CONFIG1 = $16 
	 */
	
	MFC0_SEL_OPCODE( 25, 16, C0_CONFIG1_SEL )     

#define config1	t9

	/* 
	 * I-cache lines
	 * Calculated as associativity * sets per way
	 */
	li	t8, C0_CONFIG1_IA_MSK
	and	t8, config1
	li	t7, C0_CONFIG1_IA_SHF
	srl	t8, t7
	addiu	t8,1				/* t8 = associativity	*/

	li	t7, C0_CONFIG1_IS_MSK
	and	t7, config1
	li	t9, C0_CONFIG1_IS_SHF
	srl	t7, t9
	li	t9, 0x40
	sll	t7, t9, t7			/* t7 = sets per way	*/

	multu	t8, t7
	MFLO(   v0 )

	jr	ra
	nop

icache_lines_qed_rm5261:
	li	v0, (QED_RM5261_ICACHE_SIZE / QED_RM5261_ICACHE_LSIZE)
	jr	ra
	nop

END(sys_determine_icache_lines_flash)


/************************************************************************
 *
 *                          sys_determine_icache_assoc_flash
 *  Description :
 *  -------------
 *
 *  Determine ICACHE associativity
 *
 *  input : a0 = processor ID
 *	
 *  Return values :
 *  ---------------
 *
 *  v0 = ICACHE associativity
 *
 ************************************************************************/
LEAF(sys_determine_icache_assoc_flash)	

	/* Check if it is a MIPS32/64 processor */	
	li      t9, C0_PRID_COMP_MSK
	and	t9, a0
	srl	t9, C0_PRID_COMP_SHF
	li	t8, C0_PRID_COMP_NOT_MIPS32_64
	bne	t9, t8, icache_assoc_mips32
	nop
	/* Not a MIPS32/64 processor */
	li	t9, QED_RM52XX
	beq	a0, t9, icache_assoc_qed_rm5261
	nop
	/* Unknown CPU */
icache_assoc_zero:
	jr	ra
	move	v0, zero

icache_assoc_mips32:
	
	/* Read CONFIG1 register, which holds implementation data
	/* t9 = $25, CONFIG1 = $16 
	 */
	
	MFC0_SEL_OPCODE( 25, 16, C0_CONFIG1_SEL )