📄 tabe.rpt
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# _LC1_A31 & !_LC2_A29 & _LC7_A29;
-- Node name is '|second:4|:206'
-- Equation name is '_LC2_A29', type is buried
_LC2_A29 = DFFE( _EQ078, GLOBAL( clk), VCC, VCC, VCC);
_EQ078 = _LC1_A31 & !_LC2_A29;
-- Node name is '|second:4|:215'
-- Equation name is '_LC5_A31', type is buried
_LC5_A31 = DFFE( _EQ079, GLOBAL( clk), VCC, VCC, VCC);
_EQ079 = _LC5_A35 & _LC8_A29
# _LC5_A31 & !Rest;
-- Node name is '|sel_clock:5|:36'
-- Equation name is '_LC8_A30', type is buried
_LC8_A30 = DFFE( _EQ080, GLOBAL( ckosp), VCC, VCC, VCC);
_EQ080 = !_LC2_A28 & _LC8_A30
# !_LC2_D25 & _LC8_A30
# _LC2_A28 & _LC2_D25 & !_LC8_A30;
-- Node name is '|sel_clock:5|:37'
-- Equation name is '_LC2_A28', type is buried
_LC2_A28 = DFFE( _EQ081, GLOBAL( ckosp), VCC, VCC, VCC);
_EQ081 = _LC2_A28 & !_LC2_D25
# !_LC2_A28 & _LC2_D25;
-- Node name is '|sel_clock:5|:38'
-- Equation name is '_LC2_D25', type is buried
_LC2_D25 = DFFE(!_LC2_D25, GLOBAL( ckosp), VCC, VCC, VCC);
-- Node name is '|sel_clock:5|:39'
-- Equation name is '_LC3_A30', type is buried
_LC3_A30 = LCELL( _EQ082);
_EQ082 = !_LC2_A28 & !_LC2_D25 & !_LC8_A30;
-- Node name is '|sel_clock:5|:48'
-- Equation name is '_LC6_A30', type is buried
_LC6_A30 = LCELL( _EQ083);
_EQ083 = !_LC2_A28 & _LC2_D25 & !_LC8_A30;
-- Node name is '|sel_clock:5|:57'
-- Equation name is '_LC5_A30', type is buried
_LC5_A30 = LCELL( _EQ084);
_EQ084 = _LC2_A28 & !_LC2_D25 & !_LC8_A30;
-- Node name is '|sel_clock:5|:66'
-- Equation name is '_LC7_A30', type is buried
_LC7_A30 = LCELL( _EQ085);
_EQ085 = _LC2_A28 & _LC2_D25 & !_LC8_A30;
-- Node name is '|sel_clock:5|:75'
-- Equation name is '_LC2_A30', type is buried
_LC2_A30 = LCELL( _EQ086);
_EQ086 = !_LC2_A28 & !_LC2_D25 & _LC8_A30;
-- Node name is '|sel_clock:5|:85'
-- Equation name is '_LC4_A30', type is buried
_LC4_A30 = LCELL( _EQ087);
_EQ087 = !_LC2_A28 & _LC2_D25 & _LC8_A30;
-- Node name is '|sel_clock:5|:95'
-- Equation name is '_LC1_A34', type is buried
_LC1_A34 = LCELL( _EQ088);
_EQ088 = _LC2_A28 & !_LC2_D25 & _LC8_A30;
-- Node name is '|sel_clock:5|:105'
-- Equation name is '_LC1_A30', type is buried
_LC1_A30 = LCELL( _EQ089);
_EQ089 = _LC2_A28 & _LC2_D25 & _LC8_A30;
-- Node name is '|sel_clock:5|:119'
-- Equation name is '_LC3_A22', type is buried
_LC3_A22 = LCELL( _EQ090);
_EQ090 = !_LC1_A30 & _LC4_A22
# _LC1_A30 & _LC4_A11;
-- Node name is '|sel_clock:5|:120'
-- Equation name is '_LC4_A34', type is buried
_LC4_A34 = LCELL( _EQ091);
_EQ091 = _LC1_A21 & !_LC1_A30
# _LC1_A30 & _LC5_A11;
-- Node name is '|sel_clock:5|:121'
-- Equation name is '_LC6_A34', type is buried
_LC6_A34 = LCELL( _EQ092);
_EQ092 = _LC1_A29 & !_LC1_A30
# _LC1_A30 & _LC6_A11;
-- Node name is '|sel_clock:5|:122'
-- Equation name is '_LC2_A36', type is buried
_LC2_A36 = LCELL( _EQ093);
_EQ093 = !_LC1_A30 & _LC5_A36
# _LC1_A30 & _LC7_A11;
-- Node name is '|sel_clock:5|:128'
-- Equation name is '_LC5_A34', type is buried
_LC5_A34 = LCELL( _EQ094);
_EQ094 = !_LC1_A34 & _LC4_A34
# _LC1_A34 & _LC3_A12;
-- Node name is '|sel_clock:5|:135'
-- Equation name is '_LC1_A36', type is buried
_LC1_A36 = LCELL( _EQ095);
_EQ095 = !_LC1_A34 & _LC3_A22
# _LC1_A12 & _LC1_A34
# _LC4_A30;
-- Node name is '|sel_clock:5|:137'
-- Equation name is '_LC7_A34', type is buried
_LC7_A34 = LCELL( _EQ096);
_EQ096 = !_LC1_A34 & _LC6_A34
# _LC1_A34 & _LC8_A12
# _LC4_A30;
-- Node name is '|sel_clock:5|:138'
-- Equation name is '_LC3_A36', type is buried
_LC3_A36 = LCELL( _EQ097);
_EQ097 = !_LC1_A34 & _LC2_A36
# _LC1_A17 & _LC1_A34
# _LC4_A30;
-- Node name is '|sel_clock:5|:143'
-- Equation name is '_LC4_A36', type is buried
_LC4_A36 = LCELL( _EQ098);
_EQ098 = _LC1_A36 & !_LC2_A30
# _LC2_A30 & _LC4_A17;
-- Node name is '|sel_clock:5|:144'
-- Equation name is '_LC3_A34', type is buried
_LC3_A34 = LCELL( _EQ099);
_EQ099 = !_LC2_A30 & !_LC4_A30 & _LC5_A34
# _LC2_A30 & _LC3_A7;
-- Node name is '|sel_clock:5|:145'
-- Equation name is '_LC2_A34', type is buried
_LC2_A34 = LCELL( _EQ100);
_EQ100 = !_LC2_A30 & _LC7_A34
# _LC2_A17 & _LC2_A30;
-- Node name is '|sel_clock:5|:146'
-- Equation name is '_LC6_A36', type is buried
_LC6_A36 = LCELL( _EQ101);
_EQ101 = !_LC2_A30 & _LC3_A36
# _LC2_A30 & _LC3_A17;
-- Node name is '|sel_clock:5|:152'
-- Equation name is '_LC6_A31', type is buried
_LC6_A31 = LCELL( _EQ102);
_EQ102 = _LC3_A34 & !_LC7_A30
# _LC6_A24 & _LC7_A30;
-- Node name is '|sel_clock:5|:154'
-- Equation name is '_LC7_A36', type is buried
_LC7_A36 = LCELL( _EQ103);
_EQ103 = _LC6_A36 & !_LC7_A30
# _LC2_A24 & _LC7_A30;
-- Node name is '|sel_clock:5|:159'
-- Equation name is '_LC7_A22', type is buried
_LC7_A22 = LCELL( _EQ104);
_EQ104 = _LC4_A36 & !_LC7_A30
# _LC4_A24 & _LC7_A30
# _LC5_A30;
-- Node name is '|sel_clock:5|:161'
-- Equation name is '_LC3_A31', type is buried
_LC3_A31 = LCELL( _EQ105);
_EQ105 = _LC2_A34 & !_LC7_A30
# _LC3_A24 & _LC7_A30
# _LC5_A30;
-- Node name is '|sel_clock:5|:167'
-- Equation name is '_LC8_A22', type is buried
_LC8_A22 = LCELL( _EQ106);
_EQ106 = !_LC6_A30 & _LC7_A22
# _LC3_A35 & _LC6_A30;
-- Node name is '|sel_clock:5|:168'
-- Equation name is '_LC2_A31', type is buried
_LC2_A31 = LCELL( _EQ107);
_EQ107 = !_LC5_A30 & !_LC6_A30 & _LC6_A31
# _LC6_A30 & _LC8_A31;
-- Node name is '|sel_clock:5|:169'
-- Equation name is '_LC1_A22', type is buried
_LC1_A22 = LCELL( _EQ108);
_EQ108 = _LC3_A31 & !_LC6_A30
# _LC6_A30 & _LC8_A35;
-- Node name is '|sel_clock:5|:170'
-- Equation name is '_LC8_A36', type is buried
_LC8_A36 = LCELL( _EQ109);
_EQ109 = !_LC5_A30 & !_LC6_A30 & _LC7_A36
# _LC6_A30 & _LC6_A35;
-- Node name is '|sel_clock:5|:175'
-- Equation name is '_LC4_A22', type is buried
_LC4_A22 = LCELL( _EQ110);
_EQ110 = !_LC3_A30 & _LC8_A22
# _LC3_A29 & _LC3_A30;
-- Node name is '|sel_clock:5|:176'
-- Equation name is '_LC1_A21', type is buried
_LC1_A21 = LCELL( _EQ111);
_EQ111 = _LC2_A31 & !_LC3_A30
# _LC3_A30 & _LC4_A29;
-- Node name is '|sel_clock:5|:177'
-- Equation name is '_LC1_A29', type is buried
_LC1_A29 = LCELL( _EQ112);
_EQ112 = _LC1_A22 & !_LC3_A30
# _LC3_A30 & _LC7_A29;
-- Node name is '|sel_clock:5|:178'
-- Equation name is '_LC5_A36', type is buried
_LC5_A36 = LCELL( _EQ113);
_EQ113 = !_LC3_A30 & _LC8_A36
# _LC2_A29 & _LC3_A30;
Project Information e:\shiyan\tabe.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
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