📄 tabe.rpt
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Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 8 0 1 0 8 8 2 0 0 0 8 2 0 0 1 1 8 0 8 0 0 0 1 8 8 8 0 0 7 8 8 103/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 8 3 0 0 0 0 0 12/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 8 0 1 0 8 8 2 0 0 0 8 2 0 0 1 1 8 0 8 1 0 0 1 8 16 11 0 0 7 8 8 115/0
Device-Specific Information: e:\shiyan\tabe.rpt
tabe
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
125 - - - -- INPUT G ^ 0 0 0 0 ckosp
55 - - - -- INPUT G ^ 0 0 0 0 clk
47 - - - 25 INPUT ^ 0 0 0 22 Rest
49 - - - 21 INPUT ^ 0 0 0 1 SETM
48 - - - 24 INPUT ^ 0 0 0 1 SETN
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\shiyan\tabe.rpt
tabe
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
118 - - - 09 OUTPUT 0 1 0 0 a
119 - - - 13 OUTPUT 0 1 0 0 b
120 - - - 14 OUTPUT 0 1 0 0 c
121 - - - 17 OUTPUT 0 1 0 0 d
122 - - - 18 OUTPUT 0 1 0 0 e
128 - - - 19 OUTPUT 0 1 0 0 f
130 - - - 22 OUTPUT 0 1 0 0 g
136 - - - 30 OUTPUT 0 1 0 0 lope0
137 - - - 30 OUTPUT 0 1 0 0 lope1
138 - - - 31 OUTPUT 0 1 0 0 lope2
140 - - - 32 OUTPUT 0 1 0 0 lope3
132 - - - 26 OUTPUT 0 1 0 0 sel0
133 - - - 28 OUTPUT 0 1 0 0 sel1
135 - - - 29 OUTPUT 0 1 0 0 sel2
117 - - - 08 OUTPUT 0 1 0 0 speak
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\shiyan\tabe.rpt
tabe
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - D 30 AND2 0 2 0 1 |baoshi:38|lpm_add_sub:148|addcore:adder|:55
- 8 - A 24 AND2 s 0 4 0 2 |baoshi:38|~15~1
- 6 - A 07 AND2 0 4 0 4 |baoshi:38|:15
- 5 - A 07 DFFE + 0 4 1 0 |baoshi:38|:28
- 5 - D 30 DFFE + 0 3 0 5 |baoshi:38|counter3 (|baoshi:38|:30)
- 3 - D 30 DFFE + 0 3 0 6 |baoshi:38|counter2 (|baoshi:38|:31)
- 4 - D 30 DFFE + 0 2 0 7 |baoshi:38|counter1 (|baoshi:38|:32)
- 2 - D 30 DFFE + 0 1 0 8 |baoshi:38|counter0 (|baoshi:38|:33)
- 3 - D 31 OR2 s 0 4 0 1 |baoshi:38|~138~1
- 2 - D 31 OR2 0 4 1 0 |baoshi:38|:144
- 6 - D 30 OR2 s 0 4 0 1 |baoshi:38|~145~1
- 1 - D 31 OR2 0 3 1 0 |baoshi:38|:145
- 7 - D 30 OR2 ! 0 4 1 1 |baoshi:38|:146
- 1 - D 30 OR2 0 4 1 0 |baoshi:38|:147
- 5 - A 22 AND2 s 0 3 0 2 |deled:1|~51~1
- 2 - A 09 OR2 0 3 1 0 |deled:1|:189
- 6 - A 22 OR2 s 0 4 0 1 |deled:1|~217~1
- 2 - A 13 OR2 0 4 1 0 |deled:1|:217
- 1 - A 13 OR2 0 4 1 0 |deled:1|:245
- 5 - A 18 OR2 0 4 1 1 |deled:1|:273
- 8 - A 18 OR2 0 4 1 0 |deled:1|:301
- 2 - A 20 OR2 0 4 1 1 |deled:1|:329
- 2 - A 22 OR2 0 4 1 0 |deled:1|:357
- 4 - A 12 OR2 ! 0 2 0 2 |hour:2|lpm_add_sub:147|addcore:adder|:55
- 1 - A 11 AND2 1 2 0 1 |hour:2|lpm_add_sub:148|addcore:adder|:55
- 8 - A 11 AND2 1 3 0 1 |hour:2|lpm_add_sub:148|addcore:adder|:59
- 5 - A 17 OR2 1 1 0 8 |hour:2|:12
- 5 - A 12 AND2 s 1 1 0 1 |hour:2|~26~1
- 7 - A 12 AND2 0 4 0 5 |hour:2|:26
- 6 - A 12 AND2 s 1 1 0 6 |hour:2|~94~1
- 4 - A 11 DFFE 0 4 0 2 |hour:2|:102
- 5 - A 11 DFFE 0 4 0 3 |hour:2|:103
- 6 - A 11 DFFE 0 4 0 4 |hour:2|:104
- 7 - A 11 DFFE 0 3 0 5 |hour:2|:105
- 3 - A 11 OR2 s 0 3 0 1 |hour:2|~136~1
- 2 - A 11 OR2 s 0 4 0 1 |hour:2|~136~2
- 2 - A 12 OR2 s 1 3 0 3 |hour:2|~136~3
- 1 - A 12 DFFE 0 4 0 3 |hour:2|:143
- 3 - A 12 DFFE 0 4 0 4 |hour:2|:144
- 8 - A 12 DFFE 0 3 0 4 |hour:2|:145
- 1 - A 17 DFFE 0 2 0 5 |hour:2|:146
- 7 - A 24 AND2 0 2 0 1 |miniter:29|lpm_add_sub:219|addcore:adder|:55
- 7 - A 07 AND2 1 2 0 1 |miniter:29|lpm_add_sub:220|addcore:adder|:55
- 1 - A 07 AND2 1 3 0 1 |miniter:29|lpm_add_sub:220|addcore:adder|:59
- 7 - A 31 OR2 1 1 0 9 |miniter:29|:13
- 2 - A 07 OR2 0 3 0 5 |miniter:29|:57
- 4 - A 07 OR2 0 2 0 3 |miniter:29|:67
- 1 - A 24 OR2 s 0 4 0 10 |miniter:29|~99~1
- 8 - A 17 OR2 1 3 0 1 |miniter:29|:143
- 8 - A 07 OR2 1 3 0 1 |miniter:29|:144
- 7 - A 17 OR2 1 3 0 1 |miniter:29|:145
- 4 - A 17 DFFE 1 4 0 5 |miniter:29|:155
- 3 - A 07 DFFE 1 4 0 6 |miniter:29|:156
- 2 - A 17 DFFE 1 4 0 5 |miniter:29|:157
- 3 - A 17 DFFE 1 3 0 5 |miniter:29|:158
- 5 - A 24 AND2 s 1 1 0 3 |miniter:29|~193~1
- 4 - A 24 DFFE 0 4 0 3 |miniter:29|:198
- 6 - A 24 DFFE 0 4 0 4 |miniter:29|:199
- 3 - A 24 DFFE 0 3 0 5 |miniter:29|:200
- 2 - A 24 DFFE 1 2 0 6 |miniter:29|:201
- 6 - A 17 DFFE 1 3 0 1 |miniter:29|:218
- 5 - A 29 OR2 0 4 0 2 |second:4|lpm_add_sub:216|addcore:adder|:69
- 1 - A 35 AND2 1 2 0 2 |second:4|lpm_add_sub:217|addcore:adder|:55
- 5 - A 35 OR2 ! 0 4 0 2 |second:4|:62
- 2 - A 35 OR2 ! 0 2 0 4 |second:4|:79
- 6 - A 29 OR2 s ! 0 4 0 2 |second:4|~104~1
- 8 - A 29 OR2 ! 1 1 0 7 |second:4|:104
- 7 - A 35 OR2 0 4 0 1 |second:4|:129
- 4 - A 31 OR2 0 3 0 1 |second:4|:130
- 4 - A 35 OR2 0 3 0 1 |second:4|:131
- 3 - A 35 DFFE + 0 3 0 3 |second:4|:160
- 8 - A 31 DFFE + 0 3 0 4 |second:4|:161
- 8 - A 35 DFFE + 0 3 0 4 |second:4|:162
- 6 - A 35 DFFE + 0 3 0 4 |second:4|:163
- 1 - A 31 AND2 s 1 1 0 7 |second:4|~195~1
- 3 - A 29 DFFE + 1 2 0 2 |second:4|:203
- 4 - A 29 DFFE + 0 3 0 3 |second:4|:204
- 7 - A 29 DFFE + 0 2 0 4 |second:4|:205
- 2 - A 29 DFFE + 0 1 0 5 |second:4|:206
- 5 - A 31 DFFE + 1 2 0 1 |second:4|:215
- 8 - A 30 DFFE + 0 2 1 8 |sel_clock:5|:36
- 2 - A 28 DFFE + 0 1 1 9 |sel_clock:5|:37
- 2 - D 25 DFFE + 0 0 1 10 |sel_clock:5|:38
- 3 - A 30 AND2 0 3 0 4 |sel_clock:5|:39
- 6 - A 30 AND2 0 3 0 4 |sel_clock:5|:48
- 5 - A 30 AND2 0 3 0 4 |sel_clock:5|:57
- 7 - A 30 AND2 0 3 0 4 |sel_clock:5|:66
- 2 - A 30 AND2 0 3 0 4 |sel_clock:5|:75
- 4 - A 30 AND2 0 3 0 4 |sel_clock:5|:85
- 1 - A 34 AND2 0 3 0 4 |sel_clock:5|:95
- 1 - A 30 AND2 0 3 0 4 |sel_clock:5|:105
- 3 - A 22 OR2 0 3 0 1 |sel_clock:5|:119
- 4 - A 34 OR2 0 3 0 1 |sel_clock:5|:120
- 6 - A 34 OR2 0 3 0 1 |sel_clock:5|:121
- 2 - A 36 OR2 0 3 0 1 |sel_clock:5|:122
- 5 - A 34 OR2 0 3 0 1 |sel_clock:5|:128
- 1 - A 36 OR2 0 4 0 1 |sel_clock:5|:135
- 7 - A 34 OR2 0 4 0 1 |sel_clock:5|:137
- 3 - A 36 OR2 0 4 0 1 |sel_clock:5|:138
- 4 - A 36 OR2 0 3 0 1 |sel_clock:5|:143
- 3 - A 34 OR2 0 4 0 1 |sel_clock:5|:144
- 2 - A 34 OR2 0 3 0 1 |sel_clock:5|:145
- 6 - A 36 OR2 0 3 0 1 |sel_clock:5|:146
- 6 - A 31 OR2 0 3 0 1 |sel_clock:5|:152
- 7 - A 36 OR2 0 3 0 1 |sel_clock:5|:154
- 7 - A 22 OR2 0 4 0 1 |sel_clock:5|:159
- 3 - A 31 OR2 0 4 0 1 |sel_clock:5|:161
- 8 - A 22 OR2 0 3 0 1 |sel_clock:5|:167
- 2 - A 31 OR2 0 4 0 1 |sel_clock:5|:168
- 1 - A 22 OR2 0 3 0 1 |sel_clock:5|:169
- 8 - A 36 OR2 0 4 0 1 |sel_clock:5|:170
- 4 - A 22 OR2 0 3 0 8 |sel_clock:5|:175
- 1 - A 21 OR2 0 3 0 9 |sel_clock:5|:176
- 1 - A 29 OR2 0 3 0 8 |sel_clock:5|:177
- 5 - A 36 OR2 0 3 0 8 |sel_clock:5|:178
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\shiyan\tabe.rpt
tabe
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 42/144( 29%) 2/ 72( 2%) 25/ 72( 34%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 1/144( 0%) 0/ 72( 0%) 6/ 72( 8%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
25: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
26: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
29: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
30: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
31: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
32: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\shiyan\tabe.rpt
tabe
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
LCELL 9 |miniter:29|:13
INPUT 8 ckosp
LCELL 8 |hour:2|:12
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