📄 sel_clock.rpt
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| | | +--------------------- LC29 out3
| | | | +------------------- LC30 sel0
| | | | | +----------------- LC26 sel1
| | | | | | +--------------- LC24 sel2
| | | | | | | +------------- LC23 ~167~1
| | | | | | | | +----------- LC22 ~168~1
| | | | | | | | | +--------- LC21 ~170~1
| | | | | | | | | | +------- LC20 ~175~1
| | | | | | | | | | | +----- LC19 ~176~1
| | | | | | | | | | | | +--- LC27 ~177~1
| | | | | | | | | | | | | +- LC18 ~178~1
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC30 -> * * * * * * * * * * * * * * | * * | <-- sel0
LC26 -> * * * * - * * * * * * * * * | * * | <-- sel1
LC24 -> * * * * - - * * * * * * * * | * * | <-- sel2
LC23 -> - - - * - - - - - - * - - - | - * | <-- ~167~1
LC22 -> - - * - - - - - - - - * - - | - * | <-- ~168~1
LC21 -> * - - - - - - - - - - - - * | - * | <-- ~170~1
LC20 -> - - - - - - - * - - - - - - | - * | <-- ~175~1
LC19 -> - - - - - - - - * - - - - - | - * | <-- ~176~1
LC18 -> - - - - - - - - - * - - - - | - * | <-- ~178~1
Pin
16 -> * - - - - - - - - - - - - * | - * | <-- A0
44 -> - * - - - - - - - - - - * - | - * | <-- A1
21 -> - - * - - - - - - - - * - - | - * | <-- A2
20 -> - - - * - - - - - - * - - - | - * | <-- A3
40 -> - - - - - - - - - * - - - - | - * | <-- B0
36 -> - - - - - - - - * - - - - - | - * | <-- B2
29 -> - - - - - - - * - - - - - - | - * | <-- B3
43 -> - - - - - - - - - - - - - - | - - | <-- ckosp
1 -> - - - - - - - - - * - - - - | - * | <-- C0
2 -> - - - - - - - - - - - - - - | * - | <-- C1
25 -> - - - - - - - - * - - - - - | - * | <-- C2
39 -> - - - - - - - * - - - - - - | - * | <-- C3
34 -> - - - - - - - - - * - - - - | - * | <-- D0
18 -> - - - - - - - - * - - - - - | - * | <-- D2
17 -> - - - - - - - * - - - - - - | - * | <-- D3
4 -> - - - - - - - - - * - - - - | - * | <-- E0
6 -> - - - - - - - - * - - - - - | - * | <-- E2
8 -> - - - - - - - * - - - - - - | - * | <-- E3
9 -> - - - - - - - - - * - - - - | - * | <-- F0
12 -> - - - - - - - - * - - - - - | - * | <-- F2
14 -> - - - - - - - * - - - - - - | - * | <-- F3
LC4 -> - * - - - - - - - - - - * - | - * | <-- ~169~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\shiyan\sel_clock.rpt
sel_clock
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
ckosp : INPUT;
C0 : INPUT;
C1 : INPUT;
C2 : INPUT;
C3 : INPUT;
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
E0 : INPUT;
E1 : INPUT;
E2 : INPUT;
E3 : INPUT;
F0 : INPUT;
F1 : INPUT;
F2 : INPUT;
F3 : INPUT;
-- Node name is 'out0'
-- Equation name is 'out0', location is LC032, type is output.
out0 = LCELL( _EQ001 $ GND);
_EQ001 = A0 & !sel0 & !sel1 & !sel2
# _LC021 & _X001;
_X001 = EXP(!sel0 & !sel1 & !sel2);
-- Node name is 'out1'
-- Equation name is 'out1', location is LC017, type is output.
out1 = LCELL( _EQ002 $ GND);
_EQ002 = A1 & !sel0 & !sel1 & !sel2
# _LC004 & _X001;
_X001 = EXP(!sel0 & !sel1 & !sel2);
-- Node name is 'out2'
-- Equation name is 'out2', location is LC028, type is output.
out2 = LCELL( _EQ003 $ GND);
_EQ003 = A2 & !sel0 & !sel1 & !sel2
# _LC022 & _X001;
_X001 = EXP(!sel0 & !sel1 & !sel2);
-- Node name is 'out3'
-- Equation name is 'out3', location is LC029, type is output.
out3 = LCELL( _EQ004 $ GND);
_EQ004 = A3 & !sel0 & !sel1 & !sel2
# _LC023 & _X001;
_X001 = EXP(!sel0 & !sel1 & !sel2);
-- Node name is 'sel0' = ':38'
-- Equation name is 'sel0', type is output
sel0 = TFFE( VCC, GLOBAL( ckosp), VCC, VCC, VCC);
-- Node name is 'sel1' = ':37'
-- Equation name is 'sel1', type is output
sel1 = TFFE( sel0, GLOBAL( ckosp), VCC, VCC, VCC);
-- Node name is 'sel2' = ':36'
-- Equation name is 'sel2', type is output
sel2 = TFFE( _EQ005, GLOBAL( ckosp), VCC, VCC, VCC);
_EQ005 = sel0 & sel1;
-- Node name is '~167~1'
-- Equation name is '~167~1', location is LC023, type is buried.
-- synthesized logic cell
_LC023 = LCELL( _EQ006 $ _EQ007);
_EQ006 = !F3 & sel0 & sel1 & sel2 & _X002 & _X003
# !E3 & !sel0 & sel1 & sel2 & _X002 & _X003
# !C3 & sel0 & sel1 & !sel2 & _X002 & _X003
# !D3 & !sel0 & !sel1 & sel2 & _X002 & _X003;
_X002 = EXP(!_LC020 & !sel0 & !sel1 & !sel2);
_X003 = EXP(!B3 & sel0 & !sel1 & !sel2);
_EQ007 = _X002 & _X003;
_X002 = EXP(!_LC020 & !sel0 & !sel1 & !sel2);
_X003 = EXP(!B3 & sel0 & !sel1 & !sel2);
-- Node name is '~168~1'
-- Equation name is '~168~1', location is LC022, type is buried.
-- synthesized logic cell
_LC022 = LCELL( _EQ008 $ _EQ009);
_EQ008 = !F2 & sel0 & sel2 & _X004 & _X005 & _X006 & _X007
# sel0 & !sel1 & sel2 & _X004 & _X005 & _X006 & _X007
# !C2 & sel1 & !sel2 & _X004 & _X005 & _X006 & _X007
# !E2 & !sel0 & sel1 & _X004 & _X005 & _X006 & _X007;
_X004 = EXP(!D2 & !sel1 & sel2);
_X005 = EXP(!sel0 & sel1 & !sel2);
_X006 = EXP(!B2 & sel0 & !sel1);
_X007 = EXP(!_LC019 & !sel0 & !sel2);
_EQ009 = _X004 & _X005 & _X006 & _X007;
_X004 = EXP(!D2 & !sel1 & sel2);
_X005 = EXP(!sel0 & sel1 & !sel2);
_X006 = EXP(!B2 & sel0 & !sel1);
_X007 = EXP(!_LC019 & !sel0 & !sel2);
-- Node name is '~169~1'
-- Equation name is '~169~1', location is LC004, type is buried.
-- synthesized logic cell
_LC004 = LCELL( _EQ010 $ _EQ011);
_EQ010 = !F1 & sel0 & sel1 & sel2 & _X008 & _X009
# !E1 & !sel0 & sel1 & sel2 & _X008 & _X009
# !C1 & sel0 & sel1 & !sel2 & _X008 & _X009
# !D1 & !sel0 & !sel1 & sel2 & _X008 & _X009;
_X008 = EXP(!_LC027 & !sel0 & !sel1 & !sel2);
_X009 = EXP(!B1 & sel0 & !sel1 & !sel2);
_EQ011 = _X008 & _X009;
_X008 = EXP(!_LC027 & !sel0 & !sel1 & !sel2);
_X009 = EXP(!B1 & sel0 & !sel1 & !sel2);
-- Node name is '~170~1'
-- Equation name is '~170~1', location is LC021, type is buried.
-- synthesized logic cell
_LC021 = LCELL( _EQ012 $ _EQ013);
_EQ012 = !F0 & sel0 & sel1 & sel2 & _X010 & _X011 & _X012
# !B0 & sel0 & !sel1 & !sel2 & _X010 & _X011 & _X012
# !D0 & !sel0 & !sel1 & sel2 & _X010 & _X011 & _X012
# !sel0 & sel1 & !sel2 & _X010 & _X011 & _X012;
_X010 = EXP(!E0 & !sel0 & sel1);
_X011 = EXP(!C0 & sel1 & !sel2);
_X012 = EXP(!_LC018 & !sel0 & !sel2);
_EQ013 = _X010 & _X011 & _X012;
_X010 = EXP(!E0 & !sel0 & sel1);
_X011 = EXP(!C0 & sel1 & !sel2);
_X012 = EXP(!_LC018 & !sel0 & !sel2);
-- Node name is '~175~1'
-- Equation name is '~175~1', location is LC020, type is buried.
-- synthesized logic cell
_LC020 = LCELL( _EQ014 $ _LC023);
_EQ014 = A3 & !_LC023 & !sel0 & !sel1 & !sel2
# !A3 & _LC023 & !sel0 & !sel1 & !sel2;
-- Node name is '~176~1'
-- Equation name is '~176~1', location is LC019, type is buried.
-- synthesized logic cell
_LC019 = LCELL( _EQ015 $ GND);
_EQ015 = A2 & !sel0 & !sel1 & !sel2
# _LC022 & _X001;
_X001 = EXP(!sel0 & !sel1 & !sel2);
-- Node name is '~177~1'
-- Equation name is '~177~1', location is LC027, type is buried.
-- synthesized logic cell
_LC027 = LCELL( _EQ016 $ GND);
_EQ016 = A1 & !sel0 & !sel1 & !sel2
# _LC004 & _X001;
_X001 = EXP(!sel0 & !sel1 & !sel2);
-- Node name is '~178~1'
-- Equation name is '~178~1', location is LC018, type is buried.
-- synthesized logic cell
_LC018 = LCELL( _EQ017 $ GND);
_EQ017 = A0 & !sel0 & !sel1 & !sel2
# _LC021 & _X001;
_X001 = EXP(!sel0 & !sel1 & !sel2);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\shiyan\sel_clock.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,757K
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