📄 second.rpt
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Logic cells placed in LAB 'B'
+------------------------------- LC21 A0
| +----------------------------- LC24 A1
| | +--------------------------- LC27 A2
| | | +------------------------- LC26 A3
| | | | +----------------------- LC19 B0
| | | | | +--------------------- LC17 B1
| | | | | | +------------------- LC23 B2
| | | | | | | +----------------- LC18 B3
| | | | | | | | +--------------- LC22 ckmin
| | | | | | | | | +------------- LC25 |lpm_add_sub:216|addcore:adder|addcore:adder0|result_node1
| | | | | | | | | | +----------- LC28 |lpm_add_sub:216|addcore:adder|addcore:adder0|result_node2
| | | | | | | | | | | +--------- LC20 |lpm_add_sub:216|addcore:adder|addcore:adder0|result_node3
| | | | | | | | | | | | +------- LC32 |lpm_add_sub:217|addcore:adder|addcore:adder0|result_node0
| | | | | | | | | | | | | +----- LC31 |lpm_add_sub:217|addcore:adder|addcore:adder0|result_node1
| | | | | | | | | | | | | | +--- LC30 |lpm_add_sub:217|addcore:adder|addcore:adder0|result_node2
| | | | | | | | | | | | | | | +- LC29 |lpm_add_sub:217|addcore:adder|addcore:adder0|result_node3
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC21 -> * - - - - - - - - * * * - - - - | - * | <-- A0
LC24 -> - - - - - - - - - * * * - - - - | - * | <-- A1
LC27 -> - - - - - - - - - - * * - - - - | - * | <-- A2
LC26 -> - - - - - - - - - - - * - - - - | - * | <-- A3
LC19 -> - - - - * * * * * - - - * * * * | - * | <-- B0
LC17 -> - - - - * * * * * - - - - * * * | - * | <-- B1
LC23 -> - - - - * * * * * - - - - - * * | - * | <-- B2
LC18 -> - - - - * * * * * - - - - - - * | - * | <-- B3
LC22 -> - - - - - - - - * - - - - - - - | - * | <-- ckmin
LC25 -> * * - * * * * * * - - - - - - - | - * | <-- |lpm_add_sub:216|addcore:adder|addcore:adder0|result_node1
LC28 -> * - * * * * * * * - - - - - - - | - * | <-- |lpm_add_sub:216|addcore:adder|addcore:adder0|result_node2
LC20 -> * * * * * * * * * - - - - - - - | - * | <-- |lpm_add_sub:216|addcore:adder|addcore:adder0|result_node3
LC32 -> - - - - * - - - - - - - - - - - | - * | <-- |lpm_add_sub:217|addcore:adder|addcore:adder0|result_node0
LC31 -> - - - - - * - - - - - - - - - - | - * | <-- |lpm_add_sub:217|addcore:adder|addcore:adder0|result_node1
LC30 -> - - - - - - * - - - - - - - - - | - * | <-- |lpm_add_sub:217|addcore:adder|addcore:adder0|result_node2
LC29 -> - - - - - - - * - - - - - - - - | - * | <-- |lpm_add_sub:217|addcore:adder|addcore:adder0|result_node3
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk
4 -> * * * * * * * * * - - - * * * * | - * | <-- Rest
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\shiyan\second.rpt
second
** EQUATIONS **
clk : INPUT;
Rest : INPUT;
-- Node name is 'A0' = ':206'
-- Equation name is 'A0', type is output
A0 = DFFE( _EQ001 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !A0 & !_LC025 & !_LC028 & Rest
# !A0 & !_LC020 & Rest;
-- Node name is 'A1' = ':205'
-- Equation name is 'A1', type is output
A1 = DFFE( _EQ002 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !_LC020 & _LC025 & Rest;
-- Node name is 'A2' = ':204'
-- Equation name is 'A2', type is output
A2 = DFFE( _EQ003 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !_LC020 & _LC028 & Rest;
-- Node name is 'A3' = ':203'
-- Equation name is 'A3', type is output
A3 = DFFE( _EQ004 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC020 & !_LC025 & !_LC028 & Rest;
-- Node name is 'B0' = ':163'
-- Equation name is 'B0', type is output
B0 = DFFE( _EQ005 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _X001 & _X002 & _X003 & _X004 & _X005 & _X006;
_X001 = EXP(!B0 & !B1 & !B3 & _LC020 & _LC028 & _LC032 & Rest);
_X002 = EXP(!B0 & !B1 & !B3 & _LC020 & _LC025 & !_LC028 & _LC032 & Rest);
_X003 = EXP(!B2 & !B3 & _LC020 & _LC025 & !_LC028 & _LC032 & Rest);
_X004 = EXP(!B2 & !B3 & _LC020 & _LC028 & _LC032 & Rest);
_X005 = EXP( B0 & !_LC025 & !_LC028 & Rest);
_X006 = EXP( B0 & !_LC020 & Rest);
-- Node name is 'B1' = ':162'
-- Equation name is 'B1', type is output
B1 = DFFE( _EQ006 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _X007 & _X008 & _X009 & _X010 & _X011 & _X012;
_X007 = EXP(!B0 & !B1 & !B3 & _LC020 & _LC028 & _LC031 & Rest);
_X008 = EXP(!B0 & !B1 & !B3 & _LC020 & _LC025 & !_LC028 & _LC031 & Rest);
_X009 = EXP(!B2 & !B3 & _LC020 & _LC025 & !_LC028 & _LC031 & Rest);
_X010 = EXP(!B2 & !B3 & _LC020 & _LC028 & _LC031 & Rest);
_X011 = EXP( B1 & !_LC025 & !_LC028 & Rest);
_X012 = EXP( B1 & !_LC020 & Rest);
-- Node name is 'B2' = ':161'
-- Equation name is 'B2', type is output
B2 = DFFE( _EQ007 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !B2 & !B3 & _LC020 & _LC025 & _LC030 & Rest
# !B2 & !B3 & _LC020 & _LC028 & _LC030 & Rest
# !B0 & !B1 & B2 & !B3 & _LC030 & Rest
# B2 & !_LC025 & !_LC028 & Rest
# B2 & !_LC020 & Rest;
-- Node name is 'B3' = ':160'
-- Equation name is 'B3', type is output
B3 = DFFE( _EQ008 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !B0 & !B1 & !B3 & _LC020 & _LC029 & Rest & _X013
# !B2 & !B3 & _LC020 & _LC029 & Rest & _X013
# B3 & !_LC025 & !_LC028 & Rest
# B3 & !_LC020 & Rest;
_X013 = EXP(!_LC025 & !_LC028);
-- Node name is 'ckmin' = ':215'
-- Equation name is 'ckmin', type is output
ckmin = DFFE( _EQ009 $ VCC, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !B0 & !B1 & !B3 & Rest
# !_LC025 & !_LC028 & Rest
# !B2 & !B3 & Rest
# !_LC020 & Rest
# !ckmin & !Rest;
-- Node name is '|lpm_add_sub:216|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried
_LC025 = LCELL(!A1 $ !A0);
-- Node name is '|lpm_add_sub:216|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC028', type is buried
_LC028 = LCELL( A2 $ _EQ010);
_EQ010 = A0 & A1;
-- Node name is '|lpm_add_sub:216|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried
_LC020 = LCELL( A3 $ _EQ011);
_EQ011 = A0 & A1 & A2;
-- Node name is '|lpm_add_sub:217|addcore:adder|addcore:adder0|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC032', type is buried
_LC032 = LCELL( _EQ012 $ VCC);
_EQ012 = B0 & Rest;
-- Node name is '|lpm_add_sub:217|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( _EQ013 $ Rest);
_EQ013 = B0 & B1 & Rest
# !B0 & !B1 & Rest;
-- Node name is '|lpm_add_sub:217|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC030', type is buried
_LC030 = LCELL( _EQ014 $ Rest);
_EQ014 = B0 & B1 & B2 & Rest
# !B0 & !B2 & Rest
# !B1 & !B2 & Rest;
-- Node name is '|lpm_add_sub:217|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried
_LC029 = LCELL( _EQ015 $ _EQ016);
_EQ015 = B3 & Rest;
_EQ016 = B0 & B1 & B2 & Rest;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\shiyan\second.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,818K
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