📄 baoshi.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\shiyan\baoshi.rpt
baoshi
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 7/144( 4%) 0/ 72( 0%) 6/ 72( 8%) 3/16( 18%) 5/16( 31%) 0/16( 0%)
D: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\shiyan\baoshi.rpt
baoshi
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 ckosp
Device-Specific Information: e:\shiyan\baoshi.rpt
baoshi
** EQUATIONS **
ckosp : INPUT;
DATA0 : INPUT;
DATA1 : INPUT;
DATA2 : INPUT;
DATA3 : INPUT;
DATA4 : INPUT;
DATA5 : INPUT;
DATA6 : INPUT;
DATA7 : INPUT;
-- Node name is ':33' = 'counter0'
-- Equation name is 'counter0', location is LC6_C27, type is buried.
counter0 = DFFE(!counter0, GLOBAL( ckosp), VCC, VCC, _LC2_C27);
-- Node name is ':32' = 'counter1'
-- Equation name is 'counter1', location is LC5_C27, type is buried.
counter1 = DFFE( _EQ001, GLOBAL( ckosp), VCC, VCC, _LC2_C27);
_EQ001 = !counter0 & counter1
# counter0 & !counter1;
-- Node name is ':31' = 'counter2'
-- Equation name is 'counter2', location is LC7_C27, type is buried.
counter2 = DFFE( _EQ002, GLOBAL( ckosp), VCC, VCC, _LC2_C27);
_EQ002 = !counter1 & counter2
# !counter0 & counter2
# counter0 & counter1 & !counter2;
-- Node name is ':30' = 'counter3'
-- Equation name is 'counter3', location is LC4_C27, type is buried.
counter3 = DFFE( _EQ003, GLOBAL( ckosp), VCC, VCC, _LC2_C27);
_EQ003 = counter3 & !_LC8_C27
# !counter2 & counter3
# counter2 & !counter3 & _LC8_C27;
-- Node name is 'lope0'
-- Equation name is 'lope0', type is output
lope0 = _LC7_C21;
-- Node name is 'lope1'
-- Equation name is 'lope1', type is output
lope1 = _LC2_C21;
-- Node name is 'lope2'
-- Equation name is 'lope2', type is output
lope2 = _LC1_C21;
-- Node name is 'lope3'
-- Equation name is 'lope3', type is output
lope3 = _LC6_C21;
-- Node name is 'speak'
-- Equation name is 'speak', type is output
speak = _LC3_C27;
-- Node name is '|lpm_add_sub:148|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C27', type is buried
_LC8_C27 = LCELL( _EQ004);
_EQ004 = counter0 & counter1;
-- Node name is '~15~1'
-- Equation name is '~15~1', location is LC1_C28, type is buried.
-- synthesized logic cell
_LC1_C28 = LCELL( _EQ005);
_EQ005 = !DATA3 & !DATA4 & !DATA5;
-- Node name is '~15~2'
-- Equation name is '~15~2', location is LC1_C27, type is buried.
-- synthesized logic cell
_LC1_C27 = LCELL( _EQ006);
_EQ006 = !DATA6 & !DATA7 & _LC1_C28;
-- Node name is ':15'
-- Equation name is '_LC2_C27', type is buried
_LC2_C27 = LCELL( _EQ007);
_EQ007 = !DATA0 & !DATA1 & !DATA2 & _LC1_C27;
-- Node name is ':28'
-- Equation name is '_LC3_C27', type is buried
_LC3_C27 = DFFE( _EQ008, GLOBAL( ckosp), VCC, VCC, VCC);
_EQ008 = !DATA0 & !DATA1 & !DATA2 & _LC1_C27;
-- Node name is '~138~1'
-- Equation name is '~138~1', location is LC3_C21, type is buried.
-- synthesized logic cell
_LC3_C21 = LCELL( _EQ009);
_EQ009 = counter1 & counter3
# counter2 & counter3
# counter0 & counter3
# counter0 & !counter1
# !counter0 & counter1;
-- Node name is ':144'
-- Equation name is '_LC6_C21', type is buried
_LC6_C21 = LCELL( _EQ010);
_EQ010 = counter0 & counter1 & counter2
# counter3;
-- Node name is '~145~1'
-- Equation name is '~145~1', location is LC4_C21, type is buried.
-- synthesized logic cell
_LC4_C21 = LCELL( _EQ011);
_EQ011 = counter0 & counter1 & !counter2 & !counter3
# !counter1 & counter2 & !counter3
# !counter0 & counter2 & !counter3;
-- Node name is ':145'
-- Equation name is '_LC1_C21', type is buried
_LC1_C21 = LCELL( _EQ012);
_EQ012 = !_LC2_C21 & _LC3_C21
# _LC4_C21;
-- Node name is ':146'
-- Equation name is '_LC2_C21', type is buried
!_LC2_C21 = _LC2_C21~NOT;
_LC2_C21~NOT = LCELL( _EQ013);
_EQ013 = counter2 & counter3
# counter1 & counter3
# !counter0 & counter3
# counter0 & counter1
# !counter0 & !counter1;
-- Node name is ':147'
-- Equation name is '_LC7_C21', type is buried
_LC7_C21 = LCELL( _EQ014);
_EQ014 = !counter0 & !counter1 & !counter2
# !counter0 & !counter3;
Project Information e:\shiyan\baoshi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 24,443K
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