si2aub4at303.dsp

基于ADSP的G.729语音编解码程序

                  ||||||||+---- SPORT1 Rx or IRQ0_n
                  |||||||+----- SPORT1 Tx or IRQ1_n
                  ||||||+------ BDMA
                  |||||+------- IRQE_n
                  ||||+-------- SPORT0 Rx
                  |||+--------- SPORT0 Tx
                  ||+---------- IRQL0_n
                  |+----------- IRQL1_n
                  +------------ IRQ2_n
*/

		i3 = BSBInBuf;
		cntr = 256;

		// Get data from BSB
		do GET_BSB until ce;

//			ax0  = io(0x703);

			ax0  = io(0x702);
			dm(i3, m1) = ax0;

			ay0  = dm(i4, m5);

			none = ax0 xor ay0;

			// If the comparison fails, flag FL0 will be set
			if ne set FL0;

			io(0x700) = ax0;

			io(0x700) = ax0;

GET_BSB :
			nop;


		reset FL0;

		ar = ar + 1;

		// Count of BSB access will be transferred to 8051 by
		// auxiliary reponse channel (DSPAUXRSP).
		RegWrite(0x70D, 0x0204, ax1);
		RegWrite(0x70E, ar,     ax1);
		RegWrite(0x70F, 0x0000, ax1);

		// Interrup BSB IRQ to 8051
		RegWrite(0x707, b#1000000000000001, ax1);
/*                        ^^^^^^^^xxxxxx||
                              |         |+--- DSP BSB interrupt to 8051
                              |         |
		                      |         +---- DSP AUX interrupt to 8051
		                      |
		                      +-------------- DSP interrupt length
*/



/////////////////////////////////////////////////////////////////////////
//                                                                     //
// Enable Audio-Buffer                                                 //
//                                                                     //
/////////////////////////////////////////////////////////////////////////
ENABLE_AUB :

		RegWrite(0x704, b#1000000000000000, ax1);
/*                        ||||||xxxxxxxx||
                          ||||||        |+--- Rx FIFO empty
                          ||||||        +---- Tx FIFO full
                          ||||||
                          |||||+------------- Rx FIFO mute
                          ||||+-------------- Tx FIFO mute
                          |||+--------------- Rx FIFO pointer reset
                          ||+---------------- Tx FIFO pointer reset
                          |+----------------- Enable Rx FIFO
                          +------------------ Enable Tx FIFO
*/


		imask = b#0100000000;		
/*                ||||||||||
                  |||||||||+--- Timer
                  ||||||||+---- SPORT1 Rx or IRQ0_n
                  |||||||+----- SPORT1 Tx or IRQ1_n
                  ||||||+------ BDMA
                  |||||+------- IRQE_n
                  ||||+-------- SPORT0 Rx
                  |||+--------- SPORT0 Tx
                  ||+---------- IRQL0_n
                  |+----------- IRQL1_n
                  +------------ IRQ2_n
*/


IDLE_LOOP :

		idle;

		nop;

		jump IDLE_LOOP;


/////////////////////////////////////////////////////////////////////////
//                                                                     //
// IRQ10 : ISR for Power-down                                          //
//                                                                     //
/////////////////////////////////////////////////////////////////////////
ISR_DspPowerDown :

		rti;


/////////////////////////////////////////////////////////////////////////
//                                                                     //
// IRQ9 : ISR for DSP Work-Mode Change (from pin "IRQ2")               //
//                                                                     //
/////////////////////////////////////////////////////////////////////////
ISR_DspWkModeChg :

		rti;


/////////////////////////////////////////////////////////////////////////
//                                                                     //
// IRQ8 : ISR for Audio Buffer Tx Water-Mark (Almost Empty)            //
//                                                                     //
/////////////////////////////////////////////////////////////////////////
ISR_AUBTxWmk :

		ena sec_reg;

		// Read Tx FIFO data count
		ax1  = io(0x701);

		ay1  = AUBTxWmk;

		none = ax1 - ay1;

		if gt jump LEAVE_AUBTX_ISR;


		i3 = BSBInBuf;
		cntr = 256;
		
		do ISR_GET_BSB until ce;

			ax0  = io(0x703);

			ax0  = io(0x702);
			dm(i3, m1) = ax0;

			ay0  = dm(i4, m5);

			none = ax0 xor ay0;

			// If the comparison fails, flag FL0 will be set
			if ne set FL0;

			io(0x700) = ax0;

			io(0x700) = ax0;

ISR_GET_BSB :	
			nop;

		
		reset FL0;		


LEAVE_AUBTX_ISR :

		dis sec_reg;

		ar = ar + 1;

		// Count of BSB access will be transfferred by
		// auxiliary response channel (DSPAUXRSP).
		RegWrite(0x70D, 0x0204, ax1);
		RegWrite(0x70E, ar,     ax1);
		RegWrite(0x70F, 0xFFEE, ax1);

		// Interrup BSB IRQ to 8051
		RegWrite(0x707, b#1000000000000001, ax1);
/*                        ^^^^^^^^xxxxxx||
                              |         |+--- DSP BSB interrupt to 8051
                              |         |
		                      |         +---- DSP AUX interrupt to 8051
		                      |
		                      +-------------- DSP interrupt length
*/

		rti;


/////////////////////////////////////////////////////////////////////////
//                                                                     //
// IRQ7 : ISR for Audio Buffer Rx Water-Mark (Almost Full)             //
//                                                                     //
/////////////////////////////////////////////////////////////////////////
ISR_AUBRxWmk :

		rti;


/////////////////////////////////////////////////////////////////////////
//                                                                     //
// IRQ4 : ISR for Bit-Stream Buffer (from pin "IRQE")                  //
//                                                                     //
/////////////////////////////////////////////////////////////////////////
ISR_AccessBSB :

		ena sec_reg;

		ax1 = 0x0001;

		dm(BSBWrRdReq) = ax1;

		dis sec_reg;

		rti;


/////////////////////////////////////////////////////////////////////////
//                                                                     //
// IRQ1 : ISR for Auxiliary Commands (from pin "IRQ0")                 //
//                                                                     //
/////////////////////////////////////////////////////////////////////////
ISR_AuxCmdDecode :

		ena sec_reg;

		// Get MICROAUXCMD0
		ay0  = io(0x709);
		dm(MicroAuxCmd0) = ay0;

		// Get MICROAUXDAT0
		ay1  = io(0x70A);
		dm(MicroAuxDat0) = ay1;

		// Get MICROAUXDAT1
		ay1  = io(0x70B);
		dm(MicroAuxDat1) = ay1;

		// Get MICROAUXDAT2
		ay1  = io(0x70C);
		dm(MicroAuxDat2) = ay1;

		// Check MSGTYP
		ar = 0xFF00;

		af = ar and ay0;

		ar = 0x0100;

		none = ar xor af;

		if eq jump GET_CMDID;

		idle;

		nop;


GET_CMDID :

		// Check CMDID
		ar = 0x00FF;
		
		af = ar and ay0;

		
CMD1:
		ar = 0x0001;
		
		none = ar xor af;
		
		if ne jump CMD2;
		
		dis sec_reg;
	
		rti;


CMD2:
		ar = 0x0002;
		
		none = ar xor af;
		
		if ne jump CMD3;

		dis sec_reg;

		rti;

		
CMD3:
		ar = 0x0003;
		
		none = ar xor af;
		
		if ne jump CMD4;

		dis sec_reg;
	
		rti;


CMD4:

		dis sec_reg;

		rti;