📄 test4at303.dsp
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#include "DspCtrlReg4AT303.h"
#include "Macros4AT303.dsp"
//#define DEBUG
/************************************************************************
* *
* REPLACEMENT OR MACRO DECLARATIONS *
* *
************************************************************************/
#define AUBSize 2048
#define AUBTxWmk 256
#define AUBRxWmk AUBSize - 3*AUBTxWmk
////////////////////////
// Constant declarations
////////////////////////
#define BIAD 0x3FE1 // BDMA internal address register
#define BEAD 0x3FE2 // BDMA external address register
#define BCONTROL 0x3FE3 // BDMA control register
#define BWCOUNT 0x3FE4 // BDMA word count register
#define BMASK 0x0008 // BDMA interrupt mask
#define BCODE 0x0020 // Words to read
#define B_EAD_CODE 0x0000 // External address
#define B_IAD_CODE 0x0000 // Internal address
#define B_CON_MP3D 0x0408 // BDMA control for Mp3decoder
#define B_CON_MP3E 0x0808 // BDMA control for Mp3encoder
#define B_CON_G729 0x0108 // BDMA control for G729decoder
#define B_CON_TOP 0x0008 // BDMA control for Top
/************************************************************************
* *
* DECLARATIONS *
* *
************************************************************************/
#define stream_port 0x702 //0x201 // compressed data
#define speech_port 0x700 //0x200 // uncompressed data
/******************************************************************
* main control program to test calc_cw code and verify cw result **
* NOTICE: some multifunction instruction may create warnings **
* when you assemble it, but it is no harm to your **
* program. So you do better verify on Emulation!!!!! **
* See created map file and verify the pm and dm data size required*
* Author: Jason wang(zhigang wang) **
* Email: wzg119@yeah.net ,BP : +8602195950-161452 **
*******************************************************************/
//.MODULE/SEG=App_PM/ABS=0x0000 test_main;
.MODULE/SEG=START_PM test_main;
/*******************************************************************/
#include "def2181.inc"
#include "Dtx.inc"
/*******************************************************************/
.VAR/DM/RAM/SEG=App_DMbuf count_frame,flag_cod,Enc_Frame;
/*******************************************************************/
.GLOBAL flag_cod,Enc_Frame;
.EXTERNAL Vad_Enable;
.EXTERNAL Init_encoder;
.EXTERNAL Init_decoder;
.EXTERNAL encode_frame;
.EXTERNAL decode_seag;
.EXTERNAL out_speech;
.EXTERNAL flush_speech;
.EXTERNAL read_seag;
!*******************************************************************
//-----------------------------------------sunny+<
//
.VAR/DM/RAM/SEG=App_DMtmp available_stream_samples, stream_current_sample_position, stream_last_sample_position;
.VAR/DM/CIRC/SEG=App_DMtmp tmp_bit_stream[296]; // 256 + (41 - 1)
// the following variables are for debug only
//.VAR/DM/RAM/SEG=App_DMtmp tmp_speech_out[8320], tmp_speech_out_position, tmp_bit_stream_read[296], tmp_bit_stream_read_position, tmp_I0, tmp_I2; //sunny+
// ----------------+< sunny
// Section in Data Memory for AT303 //
.VAR/DM/RAM/SEG=App_DMtmp MicroAuxCmd0, MicroAuxDat0, MicroAuxDat1, MicroAuxDat2;
.VAR/DM/RAM/SEG=App_DMtmp BSBInBuf[256];
.VAR/DM/RAM/SEG=App_DMtmp BSBWrRdReq;
//------------------+<Anna
.VAR/DM/RAM/SEG=App_DMtmp StartPlay,PausePlay,ResumePlay,EndPlay,AbortPlay,StartEncode,PauseEncode,ResumeEncode,EndEncode,AbortEncode,BusyFlag;
.VAR/DM/RAM/SEG=App_DMtmp Filepos_High, Filepos_Low, Skipoffset,data_throw;
.VAR/DM/RAM/SEG=App_DMtmp BSB_Number, Frame_Numbers;
//-------------------+>Anna
.INIT BSBWrRdReq: 0;
.INIT StartEncode: 0;
//-----------------------+<Anna
.INIT PauseEncode: 0;
.INIT ResumeEncode: 0;
.INIT EndEncode: 0;
.INIT AbortEncode: 0;
.INIT StartPlay: 0;
.INIT PausePlay: 0;
.INIT ResumePlay: 0;
.INIT EndPlay: 0;
.INIT AbortPlay: 0;
.INIT BusyFlag: 0x0080;
.INIT Filepos_High: 0;
.INIT Filepos_Low: 0;
.INIT Skipoffset: 0;
.INIT BSB_Number: 0;
.INIT Frame_Numbers: 0;
.INIT data_throw: 0;
//----------------------------+>Anna
.var/dm/ram/seg=App_DMtmp Workmode;
.var/dm/ram/seg=App_DMtmp WmodeChange;
.init WmodeChange:0;
// ---------------->+ sunny
.GLOBAL stream_current_sample_position, tmp_bit_stream, available_stream_samples;
//.GLOBAL tmp_speech_out_position, tmp_bit_stream_read_position, tmp_I0, tmp_I2;
JUMP START_TEST; NOP; NOP; NOP; /*reset vector*/
RTI; NOP; NOP; NOP; /*IRQ2*/
RTI; NOP; NOP; NOP; /*IRQL1*/
JUMP ISR_AuxCmdDecode; NOP; NOP; NOP; /*IRQL2*/
RTI; NOP; NOP; NOP; /*SPORT0 transmit*/
RTI; NOP; NOP; NOP; /*SPORT0 receive*/
JUMP ISR_AccessBSB; NOP; NOP; NOP; /*BSB, IRQE*/
RTI; NOP; NOP; NOP; /*BDMA*/
JUMP ISR_AUBTxWmk; NOP; NOP; NOP; /*SPORT1 transmit*/
JUMP ISR_AUBRxWmk; NOP; NOP; NOP; /*SPORT1 receive*/
RTI; NOP; NOP; NOP; /*timer*/
RTI; NOP; NOP; NOP; /*Power down*/
RTI; NOP; NOP; NOP; /*Breakpoint*/
RTI; NOP; NOP; NOP; /*WK_mode_irq*/
//-----------------------------------------+> sunny
START_TEST:
//---------------------------------+<Anna
ax1=dm(AbortPlay);
ay1=dm(AbortEncode);
none=ax1 or ay1;
if eq jump NORMAL_START_TEST;
RegWrite(0x703,0x8000,ax1);
RegWrite(0x70D,0x0000,ax1);
RegWrite(0x707,b#1000000000000010,ax1);
//----------------------------------+>Anna
//--------------------------+<Jinyan
NORMAL_START_TEST:
dis ints;
sr1=sstat;
ar=sr1 and 0x01;
if ne jump pop_cntrstack;
sr1=toppcstack;
jump START_TEST;
pop_cntrstack:
sr1=sstat;
ar=sr1 and 0x04;
if ne jump pop_statstack;
pop cntr;
jump pop_cntrstack;
pop_statstack:
sr1=sstat;
ar=sr1 and 0x10;
if ne jump pop_loopstack;
pop sts;
jump pop_statstack;
pop_loopstack:
sr1=sstat;
ar=sr1 and 0x40;
if ne jump normal_setup;
pop loop;
jump pop_loopstack;
//-----------------------------------+>Jinyan
Normal_setup:
CALL setup_system;
AR=PASS 0;
DM(count_frame)=AR;
//-------------------------------------------+< sunny
icntl = b#00111;
/* |x|||
| ||+--- IRQ0_n sensitivity (0 = level, 1 = edge)
| |+---- IRQ1_n sensitivity (0 = level, 1 = edge)
| +----- IRQ2_n sensitivity (0 = level, 1 = edge)
|
+------- Interrupt nesting (0 = disable, 1 = enable)
*/
/////////////////////////////////////////////////////////////////////////
// //
// Audio-Buffer Control Register and Water-Marker Setting //
// //
/////////////////////////////////////////////////////////////////////////
//-----------------------------------+<Anna
SEND_RSP_TO_MICRO :
RegWrite(0x70D, 0x0201, ax1);
RegWrite(0x70E, 0x0d00, ax1); // sampling rate
RegWrite(0x70F, 0x0000, ax1);
// Interrup AUX IRQ to 8051
RegWrite(0x707, b#1000000000000010, ax1);
imask = b#0010000000;
ena ints;
Main_loop:
ax1=0x3344;
io(0x555)=ax1;
idle;
nop;
dis sec_reg; //jinyan+
ar=dm(StartPlay);
none=pass ar;
if eq jump If_enc;
RegWrite(0x70D,0x0000,ax1);
RegWrite(0x707,b#1000000000000010,ax1);
AR=PASS 0;
jump Main_pro;
If_enc:
ar=dm(StartEncode);
none=pass ar;
if eq jump Main_loop;
RegWrite(0x70D,0x0000,ax1);
RegWrite(0x707,b#1000000000000010,ax1);
AR=PASS 1;
Main_pro:
//------------------------------------------+>Anna
//AR=PASS 1; { 1 to control encoder and 0 decoder}//Anna-
IF EQ JUMP _decoder_set_up;
_encoder_set_up:
AR=FLAG_COD;
DM(flag_cod)=AR;
CALL Init_encoder;
AR=PASS 0; { 1 to enable silence compression }
DM(Vad_Enable)=AR;
imask = b#0010000000;
/* ||||||||||
|||||||||+--- Timer
||||||||+---- SPORT1 Rx or IRQ0_n
|||||||+----- SPORT1 Tx or IRQ1_n
||||||+------ BDMA
|||||+------- IRQE_n
||||+-------- SPORT0 Rx
|||+--------- SPORT0 Tx
||+---------- IRQL0_n
|+----------- IRQL1_n
+------------ IRQ2_n
*/
// Setup AUBCTL (Audio-Buffer Control Register)
RegWrite(0x704, b#0011000000000000, ax1);
/* ||||||xxxxxxxx||
|||||| |+--- Rx FIFO empty
|||||| +---- Tx FIFO full
||||||
|||||+------------- Rx FIFO mute
||||+-------------- Tx FIFO mute
|||+--------------- Rx FIFO pointer reset
||+---------------- Tx FIFO pointer reset
|+----------------- Enable Rx FIFO
+------------------ Enable Tx FIFO
*/
RegWrite(0x704, 0, ax1); // toggle pointer
// Setup AUBRXWMK (Audio-Buffer Rx Watermarker)
RegWrite(0x72A, AUBRxWmk, ax1);
jump _pre_fill;
_decoder_set_up:
AR=FLAG_DEC;
DM(flag_cod)=AR;
CALL Init_decoder;
ax0 = 0;
dm(BSBWrRdReq) = ax0;
imask = b#0000010000;
/* ||||||||||
|||||||||+--- Timer
||||||||+---- SPORT1 Rx or IRQ0_n
|||||||+----- SPORT1 Tx or IRQ1_n
||||||+------ BDMA
|||||+------- IRQE_n
||||+-------- SPORT0 Rx
|||+--------- SPORT0 Tx
||+---------- IRQL0_n
|+----------- IRQL1_n
+------------ IRQ2_n
*/
// Setup AUBCTL (Audio-Buffer Control Register)
RegWrite(0x704, b#0010000000000000, ax1);
/* ||||||xxxxxxxx||
|||||| |+--- Rx FIFO empty
|||||| +---- Tx FIFO full
||||||
|||||+------------- Rx FIFO mute
||||+-------------- Tx FIFO mute
|||+--------------- Rx FIFO pointer reset
||+---------------- Tx FIFO pointer reset
|+----------------- Enable Rx FIFO
+------------------ Enable Tx FIFO
*/
// RegWrite(0x704, 0, ax1); // toggle pointer //Anna-
RegWrite(0x704, b#0000100000000000, ax1); //Anna+ to enable Tx FIFO mute
_pre_fill:
// Pre-fill an mount of "dummy" data to pull the pin "IRQL1" down
ax0=0;
cntr =2048;
do DUMMY_FILL until ce;
DUMMY_FILL :
io(0x700) = ax0;
// Setup AUBTXWMK (Audio-Buffer Tx Watermarker)
RegWrite(0x729, AUBTxWmk, ax1);
/////////////////////////////////////////////////////////////////////////
// //
// Response 8051 to indicate that DSP initialization is done //
// //
/////////////////////////////////////////////////////////////////////////
//SEND_RSP_TO_MICRO : //Anna-
// Responce message
// --------------------------------------------------------------
// Byte 0 : 0x02 MSGTYP Message type
// Byte 1 : 0x01 RSPID Response ID
// Byte 2 : 0x01 Fs Sampling Frequency
// 0x01 = 44.1 KHz
// 0x04 = 22.05 KHz
// Byte 3 : 0x00
// Byte 4 : 0x00
// Byte 5 : 0x00
//
// RegWrite(0x70D, 0x0201, ax1);
// RegWrite(0x70E, 0x0d00, ax1); // sampling rate
// RegWrite(0x70F, 0x0000, ax1);
// Interrup AUX IRQ to 8051
// RegWrite(0x707, b#1000000000000010, ax1);
/* ^^^^^^^^xxxxxx||
| |+--- DSP BSB interrupt to 8051
| |
| +---- DSP AUX interrupt to 8051
|
+-------------- DSP interrupt length
*/
AR=DM(flag_cod);
none = pass ar;
if eq jump WAIT_BSB_IRQ;
/////////////////////////////////////////////////////////////////////////
// //
// Force DSP to wait for commands to start encoding //
// //
/////////////////////////////////////////////////////////////////////////
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< sunny +
I0 = ^tmp_bit_stream;
DM(stream_current_sample_position) = I0;
DM(stream_last_sample_position) = I0;
AY0 = 0; // no encoded samples
DM(available_stream_samples) = AY0;
//>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> sunny +
WAIT_FOR_ENC_CMD :
ax1 = dm(StartEncode);
none = pass ax1;
if ne jump ENCODER_ENABLE_AUB;
idle;
jump WAIT_FOR_ENC_CMD;
ENCODER_ENABLE_AUB :
// ax1 = 0; //Anna-
// dm(StartEncode) = ax1; //Anna-
RegWrite(0x704, b#1100000000000000, ax1);
/* ||||||xxxxxxxx||
|||||| |+--- Rx FIFO empty
|||||| +---- Tx FIFO full
||||||
|||||+------------- Rx FIFO mute
||||+-------------- Tx FIFO mute
|||+--------------- Rx FIFO pointer reset
||+---------------- Tx FIFO pointer reset
|+----------------- Enable Rx FIFO
+------------------ Enable Tx FIFO
*/
imask = b#0000000010;
/* ||||||||||
|||||||||+--- Timer
||||||||+---- SPORT1 Rx or IRQ0_n
|||||||+----- SPORT1 Tx or IRQ1_n
||||||+------ BDMA
|||||+------- IRQE_n
||||+-------- SPORT0 Rx
|||+--------- SPORT0 Tx
||+---------- IRQL0_n
|+----------- IRQL1_n
+------------ IRQ2_n
*/
jump IDLE_LOOP_ENC;
/////////////////////////////////////////////////////////////////////////
// //
// Force DSP to wait for BSB interrupt from 8051 //
// //
/////////////////////////////////////////////////////////////////////////
WAIT_BSB_IRQ :
ax1 = dm(BSBWrRdReq);
ay1 = 0x0001;
none = ax1 xor ay1;
if eq jump DIS_BSB_IRQ;
idle;
jump WAIT_BSB_IRQ;
DIS_BSB_IRQ :
ax1 = 0;
dm(BSBWrRdReq) = ax1;
imask = b#0000000000;
/* ||||||||||
|||||||||+--- Timer
||||||||+---- SPORT1 Rx or IRQ0_n
|||||||+----- SPORT1 Tx or IRQ1_n
||||||+------ BDMA
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