songer.vhd

来自「v h d l 编程」· VHDL 代码 · 共 35 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Songer IS                                     -- 顶层设计
    PORT (   CLK12MHZ : IN STD_LOGIC;
             CLK8HZ   : IN STD_LOGIC; 
               CODE1  : OUT INTEGER RANGE 0 TO 15;
               HIGH1  : OUT STD_LOGIC; 
             SPKOUT   : OUT STD_LOGIC );
 END;
ARCHITECTURE one OF Songer IS
    COMPONENT NoteTabs
        PORT (   clk  : IN STD_LOGIC;
            ToneIndex : OUT INTEGER RANGE 0 TO 15  );
    END COMPONENT;
    COMPONENT ToneTaba
        PORT ( Index :  IN INTEGER RANGE 0 TO 15;
               CODE  : OUT INTEGER RANGE 0 TO 15;
               HIGH  : OUT STD_LOGIC; 
                Tone : OUT INTEGER RANGE 0 TO 16#7FF#   ); --11位2进制数
    END COMPONENT;
    COMPONENT Speakera
        PORT (  clk  : IN STD_LOGIC;
          Tone : IN INTEGER RANGE 0 TO 16#7FF#;             --11位2进制数
          SpkS : OUT STD_LOGIC  );
    END COMPONENT;
    SIGNAL Tone : INTEGER RANGE 0 TO 16#7FF#;
    SIGNAL ToneIndex : INTEGER RANGE 0 TO 15;
BEGIN
                    -- 安装U1, U2, U3
u1 : NoteTabs  PORT MAP (clk=>CLK8HZ, ToneIndex=>ToneIndex);
u2 : ToneTaba PORT MAP (Index=>ToneIndex, Tone=>Tone,CODE=>CODE1,HIGH=>HIGH1);
u3 : Speakera PORT MAP(clk=>CLK12MHZ,Tone=>Tone, SpkS=>SPKOUT );
END;