📄 训练项目十三:基于dds芯片ad9851的信号源.s
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.module _训练项目十三:基于DDS芯片AD9851的信号源.c
.area text(rom, con, rel)
; i -> R20,R21
; uin -> R16,R17
.even
_Delay::
st -y,R20
st -y,R21
; #include"iom128v.h"
; #include"macros.h"
;
; #define SetW_CLK PORTC|=BIT(PC1)
; #define ClrW_CLK PORTC&=~BIT(PC1)
; #define SetFQ_UD PORTC|=BIT(PC0)
; #define ClrFQ_UD PORTC&=~BIT(PC0)
;
; void Delay (unsigned int uin)
; {
; int i;
;
; for(i=0; i<uin; i++) {
clr R20
clr R21
xjmp L5
L2:
; ;
; }
L3:
subi R20,255 ; offset = 1
sbci R21,255
L5:
cp R20,R16
cpc R21,R17
brlo L2
X0:
L1:
.dbline 0 ; func end
ld R21,y+
ld R20,y+
ret
; i -> R16,R17
.even
_Delay_1ms::
; }
;
; void Delay_1ms (void)
; {
; unsigned int i;
;
; for (i=0; i<2260; i++);
clr R16
clr R17
xjmp L10
L7:
L8:
subi R16,255 ; offset = 1
sbci R17,255
L10:
cpi R16,212
ldi R30,8
cpc R17,R30
brlo L7
X1:
L6:
.dbline 0 ; func end
ret
; i -> R20,R21
; uin -> R10,R11
.even
_Delay_nms::
xcall push_xgset300C
movw R10,R16
; }
;
; void Delay_nms (unsigned int uin)
; {
; unsigned int i=0;
clr R20
clr R21
;
; for (i=0;i<uin;i++){
xjmp L15
L12:
; Delay_1ms();
xcall _Delay_1ms
; }
L13:
subi R20,255 ; offset = 1
sbci R21,255
L15:
cp R20,R10
cpc R21,R11
brlo L12
X2:
L11:
.dbline 0 ; func end
xjmp pop_xgset300C
; i -> R20,R21
; uin -> R10,R11
.even
_Delay_ms::
xcall push_xgset300C
movw R10,R16
; }
;
; void Delay_ms (unsigned int uin)
; {
; int i;
;
; for(i=0;i<uin;i++){
clr R20
clr R21
xjmp L20
L17:
; Delay_nms(1000);
ldi R16,1000
ldi R17,3
xcall _Delay_nms
; }
L18:
subi R20,255 ; offset = 1
sbci R21,255
L20:
cp R20,R10
cpc R21,R11
brlo L17
X3:
L16:
.dbline 0 ; func end
xjmp pop_xgset300C
.even
_Init9851::
; }
;
; void Init9851()
; {
; DDRC|=0x03;
in R24,0x14
ori R24,3
out 0x14,R24
; DDRB|=0x01;
sbi 0x17,0
; PORTB=0xff;
ldi R24,255
out 0x18,R24
;
; ClrW_CLK ;
cbi 0x15,1
; ClrFQ_UD;
cbi 0x15,0
; Delay(2);
ldi R16,2
ldi R17,0
xcall _Delay
;
; SetW_CLK ;
sbi 0x15,1
; Delay(2);
ldi R16,2
ldi R17,0
xcall _Delay
;
; ClrW_CLK ;
cbi 0x15,1
; Delay(5);
ldi R16,5
ldi R17,0
xcall _Delay
;
; SetFQ_UD ;
sbi 0x15,0
; Delay(2);
ldi R16,2
ldi R17,0
xcall _Delay
;
; ClrFQ_UD;
cbi 0x15,0
L21:
.dbline 0 ; func end
ret
; i -> R20
; uldds -> y+1
.even
_WriteAD9851::
xcall push_arg4
st -y,R20
; }
;
; void WriteAD9851 (unsigned long int uldds)
; {
; unsigned char i;
;
; ClrW_CLK ;
cbi 0x15,1
; ClrFQ_UD;
cbi 0x15,0
;
; for(i=0;i<40;i++){
clr R20
xjmp L26
L23:
; ClrW_CLK ;
cbi 0x15,1
; if(uldds&0x000000001||i==32)
ldd R2,y+1
ldd R3,y+2
ldd R4,y+3
ldd R5,y+4
mov R30,R2
andi R30,1
brne L29
X4:
cpi R20,32
brne L27
X5:
L29:
; PORTB|=0x01;
sbi 0x18,0
xjmp L28
L27:
; else
; PORTB&=0x00;
clr R2
out 0x18,R2
L28:
; SetW_CLK ;
sbi 0x15,1
; uldds=uldds>>1;
ldd R2,y+1
ldd R3,y+2
ldd R4,y+3
ldd R5,y+4
lsr R5
ror R4
ror R3
ror R2
std y+1,R2
std y+2,R3
std y+3,R4
std y+4,R5
; }
L24:
inc R20
L26:
cpi R20,40
brlo L23
X6:
; SetFQ_UD ;
sbi 0x15,0
; ClrW_CLK ;
cbi 0x15,1
; Delay(5);
ldi R16,5
ldi R17,0
xcall _Delay
; ClrFQ_UD;
cbi 0x15,0
L22:
.dbline 0 ; func end
ld R20,y+
adiw R28,4
ret
; uldds -> y+0
; ulfreq -> y+4
.even
_Write_freq::
xcall push_arg4
sbiw R28,4
; }
;
; void Write_freq (unsigned long int ulfreq)
; {
; unsigned long uldds;
;
; uldds=ulfreq*29.82617;
ldi R16,<L31
ldi R17,>L31
xcall elpm32
movw R2,R16
movw R4,R18
ldd R16,y+4
ldd R17,y+5
ldd R18,y+6
ldd R19,y+7
xcall ulong2fp
st -y,R19
st -y,R18
st -y,R17
st -y,R16
movw R16,R2
movw R18,R4
xcall fpmule2
xcall fpint
std y+0,R16
std y+1,R17
std y+2,R18
std y+3,R19
; WriteAD9851(uldds);
ldd R16,y+0
ldd R17,y+1
ldd R18,y+2
ldd R19,y+3
xcall _WriteAD9851
L30:
.dbline 0 ; func end
adiw R28,8
ret
; i -> y+0
.even
_main::
sbiw R28,4
; }
;
; void main()
; {
; unsigned long i;
; i=100;
ldi R24,100
ldi R25,0
ldi R26,0
ldi R27,0
std y+0,R24
std y+1,R25
std y+2,R26
std y+3,R27
;
; Init9851 ();
xcall _Init9851
; Write_freq (20000000);
ldi R16,0
ldi R17,45
ldi R18,49
ldi R19,1
xcall _Write_freq
L32:
.dbline 0 ; func end
adiw R28,4
ret
.area lit(rom, con, rel)
L31:
.word 0x9bff,0x41ee
; }
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