light.v

来自「verilog语言实现交通灯」· Verilog 代码 · 共 82 行

module light(state,count1,count2,TS,TL,ST,h,f,clk,reset,C);
output reg [1:0] state;
output reg [1:0] h,f;
output reg [5:0] count1,count2;
output reg ST;
output TS,TL;
wire w;
input clk,reset,C;
reg [1:0] next_state;
reg TS,TL;

parameter HG=2'b00,HY=2'b01,FG=2'b10,FY=2'b11;
parameter TRUE=1'b1,FAULT=1'b0;

always @(posedge clk or posedge reset)
begin 
    if (reset) 
         state <= HG;      
    else state <=next_state;
end

always @(state or TL or TS or C)
begin
case(state)
 HG:begin
      if(~(TL&C)) next_state<=HG;
      else next_state<=HY;
    end
 HY:begin
      if(~TS) next_state<=HY;
      else next_state<=FG;
    end
 FG:begin
      if(~(~C|TL)) next_state<=FG;
      else next_state<=FY;
    end
 FY:begin
      if(~TS) next_state<=FY;
      else next_state<=HG;
    end
 default:next_state<=HG;
endcase
end

assign w=(TS&state[0])|(~C&~state[0]&state[1])|(C&TL&~state[0]);
//function similar to st,and the one on ppt is wrong! 
always @(posedge clk)
	ST<=w;
	
always @(posedge clk)
begin
	  h[1]=state[1];
	  h[0]=~state[1]&state[0];
	  f[1]=~state[1];
	  f[0]=state[1]&state[0];
end

always @(posedge clk)
begin
   if(w) count1<=0;
   else count1<=count1+1;
end

always @(posedge clk)
begin
   if(w) count2<=0;
   else count2<=count2+1;
end

always @(count1,ST)
begin
if(ST) TL<=0;
else TL<=(count1>=5)?TRUE:FAULT;//maybe computer doesn't tell 1 from 1'b1
end
always @(count2,reset)
begin
if(reset) TS<=0;
else TS<=(count2==2)?TRUE:FAULT;
end

endmodule