📄 prbs_5bits.mdl
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DefineNamingRule "None"
ParamNamingRule "None"
SignalNamingRule "None"
InsertBlockDesc off
SimulinkBlockComments on
EnableCustomComments off
InlinedPrmAccess "Literals"
ReqsInCode off
}
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Cell "CombineOutputUpdateFcns"
Cell "SuppressErrorStatus"
Cell "ERTCustomFileBanners"
Cell "GenerateSampleERTMain"
Cell "GenerateTestInterfaces"
Cell "ModelStepFunctionPrototypeControlComp"
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Cell "MultiInstanceERTCode"
Cell "PurelyIntegerCode"
Cell "SupportNonFinite"
Cell "SupportComplex"
Cell "SupportAbsoluteTime"
Cell "SupportContinuousTime"
Cell "SupportNonInlinedSFcns"
Cell "PortableWordSizes"
PropName "DisabledProps"
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Version "1.2.0"
TargetFcnLib "ansi_tfl_tmw.mat"
TargetLibSuffix ""
TargetPreCompLibLocation ""
GenFloatMathFcnCalls "ANSI_C"
UtilityFuncGeneration "Auto"
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GenerateSampleERTMain off
GenerateTestInterfaces off
IsPILTarget off
ModelReferenceCompliant on
IncludeMdlTerminateFcn on
CombineOutputUpdateFcns off
SuppressErrorStatus off
IncludeFileDelimiter "Auto"
ERTCustomFileBanners off
SupportAbsoluteTime on
LogVarNameModifier "rt_"
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SupportNonFinite on
SupportComplex on
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SupportContinuousTime on
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EnableShiftOperators on
ParenthesesLevel "Nominal"
PortableWordSizes off
ModelStepFunctionPrototypeControlCompliant off
ExtMode off
ExtModeStaticAlloc off
ExtModeTesting off
ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
ExtModeIntrfLevel "Level1"
RTWCAPISignals off
RTWCAPIParams off
RTWCAPIStates off
GenerateASAP2 off
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PropName "Components"
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PropName "Components"
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BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Logic
Operator "AND"
Inputs "2"
IconShape "rectangular"
AllPortsSameDT on
OutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
SampleTime "-1"
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
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Block {
BlockType Scope
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TickLabels "OneTimeTick"
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Grid "on"
TimeRange "auto"
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YMax "5"
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SaveName "ScopeData"
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MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "-1"
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Block {
BlockType SubSystem
ShowPortLabels "FromPortIcon"
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PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
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Block {
BlockType UnitDelay
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RTWStateStorageClass "Auto"
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AnnotationDefaults {
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FontWeight "normal"
FontAngle "normal"
UseDisplayTextAsClickCallback off
}
LineDefaults {
FontName "Arial"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "prbs_5bits"
Location [369, 349, 1072, 782]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
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ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Scope
Name "Scope"
Ports [1]
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Floating off
Location [188, 390, 512, 629]
Open off
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType SubSystem
Name "prbs_5bits"
Ports [0, 1]
Position [270, 100, 310, 160]
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
FunctionWithSeparateData off
MaskHideContents off
System {
Name "prbs_5bits"
Location [2, 84, 1278, 971]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
Block {
BlockType Logic
Name "Logical\nOperator"
Ports [2, 1]
Position [55, 122, 85, 153]
Orientation "left"
Operator "XOR"
AllPortsSameDT off
OutDataTypeMode "Boolean"
}
Block {
BlockType UnitDelay
Name "delay_1"
Position [55, 28, 90, 62]
X0 "1"
SampleTime "TS_PRBS"
}
Block {
BlockType UnitDelay
Name "delay_2"
Position [115, 28, 150, 62]
X0 "1"
SampleTime "-1"
}
Block {
BlockType UnitDelay
Name "delay_3"
Position [175, 28, 210, 62]
X0 "1"
SampleTime "-1"
}
Block {
BlockType UnitDelay
Name "delay_4"
Position [235, 28, 270, 62]
X0 "1"
SampleTime "-1"
}
Block {
BlockType UnitDelay
Name "delay_5"
Position [295, 28, 330, 62]
X0 "1"
SampleTime "-1"
}
Block {
BlockType Outport
Name "Out1"
Position [395, 38, 425, 52]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "delay_5"
SrcPort 1
Points [30, 0]
Branch {
Points [0, 100]
DstBlock "Logical\nOperator"
DstPort 2
}
Branch {
DstBlock "Out1"
DstPort 1
}
}
Line {
SrcBlock "delay_2"
SrcPort 1
DstBlock "delay_3"
DstPort 1
}
Line {
SrcBlock "delay_3"
SrcPort 1
Points [5, 0]
Branch {
DstBlock "delay_4"
DstPort 1
}
Branch {
Points [0, 85]
DstBlock "Logical\nOperator"
DstPort 1
}
}
Line {
SrcBlock "delay_4"
SrcPort 1
DstBlock "delay_5"
DstPort 1
}
Line {
SrcBlock "delay_1"
SrcPort 1
DstBlock "delay_2"
DstPort 1
}
Line {
SrcBlock "Logical\nOperator"
SrcPort 1
Points [-20, 0; 0, -95]
DstBlock "delay_1"
DstPort 1
}
Annotation {
Name "5 bits pseudo-random binary sequence genera"
"tor.\nThe TS_PRBS period must be defined. "
Position [154, 227]
}
}
}
Block {
BlockType Outport
Name "Out1"
Position [390, 123, 420, 137]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "prbs_5bits"
SrcPort 1
Points [25, 0]
Branch {
DstBlock "Out1"
DstPort 1
}
Branch {
Points [0, 100]
DstBlock "Scope"
DstPort 1
}
}
}
}
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