dds_project.map.qmsg

频率计 等精度频率计 可以用于频率测试的等精度频率计 可用的

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 11 20:12:50 2008 " "Info: Processing started: Sun May 11 20:12:50 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DDS_Project -c DDS_Project " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDS_Project -c DDS_Project" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sum32.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file sum32.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sum32-art " "Info: Found design unit 1: sum32-art" {  } { { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 26 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sum32 " "Info: Found entity 1: sum32" {  } { { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 19 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reg1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file reg1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg1-art " "Info: Found design unit 1: reg1-art" {  } { { "reg1.vhd" "" { Text "D:/FPGA/DDS_Project/reg1.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 reg1 " "Info: Found entity 1: reg1" {  } { { "reg1.vhd" "" { Text "D:/FPGA/DDS_Project/reg1.vhd" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "reg2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file reg2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 reg2-art " "Info: Found design unit 1: reg2-art" {  } { { "reg2.vhd" "" { Text "D:/FPGA/DDS_Project/reg2.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 reg2 " "Info: Found entity 1: reg2" {  } { { "reg2.vhd" "" { Text "D:/FPGA/DDS_Project/reg2.vhd" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adder32.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file adder32.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adder32-art " "Info: Found design unit 1: adder32-art" {  } { { "adder32.vhd" "" { Text "D:/FPGA/DDS_Project/adder32.vhd" 25 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 adder32 " "Info: Found entity 1: adder32" {  } { { "adder32.vhd" "" { Text "D:/FPGA/DDS_Project/adder32.vhd" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dds.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dds-art " "Info: Found design unit 1: dds-art" {  } { { "dds.vhd" "" { Text "D:/FPGA/DDS_Project/dds.vhd" 26 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 dds " "Info: Found entity 1: dds" {  } { { "dds.vhd" "" { Text "D:/FPGA/DDS_Project/dds.vhd" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "romtab.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file romtab.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 romtab-arc_rom " "Info: Found design unit 1: romtab-arc_rom" {  } { { "romtab.vhd" "" { Text "D:/FPGA/DDS_Project/romtab.vhd" 29 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 romtab " "Info: Found entity 1: romtab" {  } { { "romtab.vhd" "" { Text "D:/FPGA/DDS_Project/romtab.vhd" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DDS " "Info: Elaborating entity \"DDS\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sum32 sum32:u1 " "Info: Elaborating entity \"sum32\" for hierarchy \"sum32:u1\"" {  } { { "dds.vhd" "u1" { Text "D:/FPGA/DDS_Project/dds.vhd" 78 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "temp sum32.vhd(40) " "Warning (10492): VHDL Process Statement warning at sum32.vhd(40): signal \"temp\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 40 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg1 reg1:u2 " "Info: Elaborating entity \"reg1\" for hierarchy \"reg1:u2\"" {  } { { "dds.vhd" "u2" { Text "D:/FPGA/DDS_Project/dds.vhd" 79 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adder32 adder32:u3 " "Info: Elaborating entity \"adder32\" for hierarchy \"adder32:u3\"" {  } { { "dds.vhd" "u3" { Text "D:/FPGA/DDS_Project/dds.vhd" 80 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "b adder32.vhd(35) " "Warning (10492): VHDL Process Statement warning at adder32.vhd(35): signal \"b\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "adder32.vhd" "" { Text "D:/FPGA/DDS_Project/adder32.vhd" 35 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reg2 reg2:u4 " "Info: Elaborating entity \"reg2\" for hierarchy \"reg2:u4\"" {  } { { "dds.vhd" "u4" { Text "D:/FPGA/DDS_Project/dds.vhd" 81 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "romtab romtab:u5 " "Info: Elaborating entity \"romtab\" for hierarchy \"romtab:u5\"" {  } { { "dds.vhd" "u5" { Text "D:/FPGA/DDS_Project/dds.vhd" 82 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/lpm_rom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/lpm_rom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom " "Info: Found entity 1: lpm_rom" {  } { { "lpm_rom.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_rom.tdf" 43 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom romtab:u5\|lpm_rom:lpm_rom_component " "Info: Elaborating entity \"lpm_rom\" for hierarchy \"romtab:u5\|lpm_rom:lpm_rom_component\"" {  } { { "romtab.vhd" "lpm_rom_component" { Text "D:/FPGA/DDS_Project/romtab.vhd" 51 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "romtab:u5\|lpm_rom:lpm_rom_component " "Info: Elaborated megafunction instantiation \"romtab:u5\|lpm_rom:lpm_rom_component\"" {  } { { "romtab.vhd" "" { Text "D:/FPGA/DDS_Project/romtab.vhd" 51 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/altrom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/altrom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altrom " "Info: Found entity 1: altrom" {  } { { "altrom.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altrom.tdf" 77 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom romtab:u5\|lpm_rom:lpm_rom_component\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"romtab:u5\|lpm_rom:lpm_rom_component\|altrom:srom\"" {  } { { "lpm_rom.tdf" "srom" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_rom.tdf" 54 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}