dds_project.hier_info

频率计 等精度频率计 可以用于频率测试的等精度频率计 可用的

clk => b[7].CLK
clk => b[6].CLK
clk => b[5].CLK
clk => b[4].CLK
clk => b[3].CLK
clk => b[2].CLK
clk => b[1].CLK
clk => b[0].CLK
en => b[0].ENA
en => b[1].ENA
en => b[2].ENA
en => b[3].ENA
en => b[4].ENA
en => b[5].ENA
en => b[6].ENA
en => b[7].ENA
en => b[8].ENA
en => b[9].ENA
en => b[10].ENA
en => b[11].ENA
en => b[12].ENA
en => b[13].ENA
en => b[14].ENA
en => b[15].ENA
en => b[16].ENA
en => b[17].ENA
en => b[18].ENA
en => b[19].ENA
en => b[20].ENA
en => b[21].ENA
en => b[22].ENA
en => b[23].ENA
en => b[24].ENA
en => b[25].ENA
en => b[26].ENA
en => b[27].ENA
en => b[28].ENA
en => b[29].ENA
en => b[30].ENA
en => b[31].ENA
out2[0] <= b[0].DB_MAX_OUTPUT_PORT_TYPE
out2[1] <= b[1].DB_MAX_OUTPUT_PORT_TYPE
out2[2] <= b[2].DB_MAX_OUTPUT_PORT_TYPE
out2[3] <= b[3].DB_MAX_OUTPUT_PORT_TYPE
out2[4] <= b[4].DB_MAX_OUTPUT_PORT_TYPE
out2[5] <= b[5].DB_MAX_OUTPUT_PORT_TYPE
out2[6] <= b[6].DB_MAX_OUTPUT_PORT_TYPE
out2[7] <= b[7].DB_MAX_OUTPUT_PORT_TYPE
out2[8] <= b[8].DB_MAX_OUTPUT_PORT_TYPE
out2[9] <= b[9].DB_MAX_OUTPUT_PORT_TYPE
out2[10] <= b[10].DB_MAX_OUTPUT_PORT_TYPE
out2[11] <= b[11].DB_MAX_OUTPUT_PORT_TYPE
out2[12] <= b[12].DB_MAX_OUTPUT_PORT_TYPE
out2[13] <= b[13].DB_MAX_OUTPUT_PORT_TYPE
out2[14] <= b[14].DB_MAX_OUTPUT_PORT_TYPE
out2[15] <= b[15].DB_MAX_OUTPUT_PORT_TYPE
out2[16] <= b[16].DB_MAX_OUTPUT_PORT_TYPE
out2[17] <= b[17].DB_MAX_OUTPUT_PORT_TYPE
out2[18] <= b[18].DB_MAX_OUTPUT_PORT_TYPE
out2[19] <= b[19].DB_MAX_OUTPUT_PORT_TYPE
out2[20] <= b[20].DB_MAX_OUTPUT_PORT_TYPE
out2[21] <= b[21].DB_MAX_OUTPUT_PORT_TYPE
out2[22] <= b[22].DB_MAX_OUTPUT_PORT_TYPE
out2[23] <= b[23].DB_MAX_OUTPUT_PORT_TYPE
out2[24] <= b[24].DB_MAX_OUTPUT_PORT_TYPE
out2[25] <= b[25].DB_MAX_OUTPUT_PORT_TYPE
out2[26] <= b[26].DB_MAX_OUTPUT_PORT_TYPE
out2[27] <= b[27].DB_MAX_OUTPUT_PORT_TYPE
out2[28] <= b[28].DB_MAX_OUTPUT_PORT_TYPE
out2[29] <= b[29].DB_MAX_OUTPUT_PORT_TYPE
out2[30] <= b[30].DB_MAX_OUTPUT_PORT_TYPE
out2[31] <= b[31].DB_MAX_OUTPUT_PORT_TYPE


|DDS|reg2:u4
e[0] => p[0]~reg0.DATAIN
e[1] => p[1]~reg0.DATAIN
e[2] => p[2]~reg0.DATAIN
e[3] => p[3]~reg0.DATAIN
e[4] => p[4]~reg0.DATAIN
e[5] => p[5]~reg0.DATAIN
e[6] => p[6]~reg0.DATAIN
e[7] => p[7]~reg0.DATAIN
e[8] => p[8]~reg0.DATAIN
e[9] => p[9]~reg0.DATAIN
e[10] => p[10]~reg0.DATAIN
e[11] => p[11]~reg0.DATAIN
e[12] => p[12]~reg0.DATAIN
e[13] => p[13]~reg0.DATAIN
e[14] => p[14]~reg0.DATAIN
e[15] => p[15]~reg0.DATAIN
e[16] => p[16]~reg0.DATAIN
e[17] => p[17]~reg0.DATAIN
e[18] => p[18]~reg0.DATAIN
e[19] => p[19]~reg0.DATAIN
e[20] => p[20]~reg0.DATAIN
e[21] => p[21]~reg0.DATAIN
e[22] => p[22]~reg0.DATAIN
e[23] => p[23]~reg0.DATAIN
e[24] => p[24]~reg0.DATAIN
e[25] => p[25]~reg0.DATAIN
e[26] => p[26]~reg0.DATAIN
e[27] => p[27]~reg0.DATAIN
e[28] => p[28]~reg0.DATAIN
e[29] => p[29]~reg0.DATAIN
e[30] => p[30]~reg0.DATAIN
e[31] => p[31]~reg0.DATAIN
clk => p[31]~reg0.CLK
clk => p[30]~reg0.CLK
clk => p[29]~reg0.CLK
clk => p[28]~reg0.CLK
clk => p[27]~reg0.CLK
clk => p[26]~reg0.CLK
clk => p[25]~reg0.CLK
clk => p[24]~reg0.CLK
clk => p[23]~reg0.CLK
clk => p[22]~reg0.CLK
clk => p[21]~reg0.CLK
clk => p[20]~reg0.CLK
clk => p[19]~reg0.CLK
clk => p[18]~reg0.CLK
clk => p[17]~reg0.CLK
clk => p[16]~reg0.CLK
clk => p[15]~reg0.CLK
clk => p[14]~reg0.CLK
clk => p[13]~reg0.CLK
clk => p[12]~reg0.CLK
clk => p[11]~reg0.CLK
clk => p[10]~reg0.CLK
clk => p[9]~reg0.CLK
clk => p[8]~reg0.CLK
clk => p[7]~reg0.CLK
clk => p[6]~reg0.CLK
clk => p[5]~reg0.CLK
clk => p[4]~reg0.CLK
clk => p[3]~reg0.CLK
clk => p[2]~reg0.CLK
clk => p[1]~reg0.CLK
clk => p[0]~reg0.CLK
p[0] <= p[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[1] <= p[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[2] <= p[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[3] <= p[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[4] <= p[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[5] <= p[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[6] <= p[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[7] <= p[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[8] <= p[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[9] <= p[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[10] <= p[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[11] <= p[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[12] <= p[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[13] <= p[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[14] <= p[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[15] <= p[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[16] <= p[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[17] <= p[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[18] <= p[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[19] <= p[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[20] <= p[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[21] <= p[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[22] <= p[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[23] <= p[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[24] <= p[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[25] <= p[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[26] <= p[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[27] <= p[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[28] <= p[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[29] <= p[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[30] <= p[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p[31] <= p[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|DDS|romtab:u5
inclock => lpm_rom:lpm_rom_component.inclock
phase_address[0] => lpm_rom:lpm_rom_component.address[0]
phase_address[1] => lpm_rom:lpm_rom_component.address[1]
phase_address[2] => lpm_rom:lpm_rom_component.address[2]
phase_address[3] => lpm_rom:lpm_rom_component.address[3]
phase_address[4] => lpm_rom:lpm_rom_component.address[4]
phase_address[5] => lpm_rom:lpm_rom_component.address[5]
phase_address[6] => lpm_rom:lpm_rom_component.address[6]
phase_address[7] => lpm_rom:lpm_rom_component.address[7]
phase_address[8] => lpm_rom:lpm_rom_component.address[8]
phase_address[9] => lpm_rom:lpm_rom_component.address[9]
q[0] <= lpm_rom:lpm_rom_component.q[0]
q[1] <= lpm_rom:lpm_rom_component.q[1]
q[2] <= lpm_rom:lpm_rom_component.q[2]
q[3] <= lpm_rom:lpm_rom_component.q[3]
q[4] <= lpm_rom:lpm_rom_component.q[4]
q[5] <= lpm_rom:lpm_rom_component.q[5]
q[6] <= lpm_rom:lpm_rom_component.q[6]
q[7] <= lpm_rom:lpm_rom_component.q[7]
q[8] <= lpm_rom:lpm_rom_component.q[8]
q[9] <= lpm_rom:lpm_rom_component.q[9]


|DDS|romtab:u5|lpm_rom:lpm_rom_component
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
address[8] => altrom:srom.address[8]
address[9] => altrom:srom.address[9]
inclock => altrom:srom.clocki
outclock => ~NO_FANOUT~
memenab => otri[9].OE
memenab => otri[8].OE
memenab => otri[7].OE
memenab => otri[6].OE
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= otri[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= otri[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= otri[9].DB_MAX_OUTPUT_PORT_TYPE


|DDS|romtab:u5|lpm_rom:lpm_rom_component|altrom:srom
address[0] => altsyncram:rom_block.address_a[0]
address[1] => altsyncram:rom_block.address_a[1]
address[2] => altsyncram:rom_block.address_a[2]
address[3] => altsyncram:rom_block.address_a[3]
address[4] => altsyncram:rom_block.address_a[4]
address[5] => altsyncram:rom_block.address_a[5]
address[6] => altsyncram:rom_block.address_a[6]
address[7] => altsyncram:rom_block.address_a[7]
address[8] => altsyncram:rom_block.address_a[8]
address[9] => altsyncram:rom_block.address_a[9]
clocki => altsyncram:rom_block.clock0
clocko => ~NO_FANOUT~
q[0] <= altsyncram:rom_block.q_a[0]
q[1] <= altsyncram:rom_block.q_a[1]
q[2] <= altsyncram:rom_block.q_a[2]
q[3] <= altsyncram:rom_block.q_a[3]
q[4] <= altsyncram:rom_block.q_a[4]
q[5] <= altsyncram:rom_block.q_a[5]
q[6] <= altsyncram:rom_block.q_a[6]
q[7] <= altsyncram:rom_block.q_a[7]
q[8] <= altsyncram:rom_block.q_a[8]
q[9] <= altsyncram:rom_block.q_a[9]


|DDS|romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_5l01:auto_generated.address_a[0]
address_a[1] => altsyncram_5l01:auto_generated.address_a[1]
address_a[2] => altsyncram_5l01:auto_generated.address_a[2]
address_a[3] => altsyncram_5l01:auto_generated.address_a[3]
address_a[4] => altsyncram_5l01:auto_generated.address_a[4]
address_a[5] => altsyncram_5l01:auto_generated.address_a[5]
address_a[6] => altsyncram_5l01:auto_generated.address_a[6]
address_a[7] => altsyncram_5l01:auto_generated.address_a[7]
address_a[8] => altsyncram_5l01:auto_generated.address_a[8]
address_a[9] => altsyncram_5l01:auto_generated.address_a[9]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_5l01:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_5l01:auto_generated.q_a[0]
q_a[1] <= altsyncram_5l01:auto_generated.q_a[1]
q_a[2] <= altsyncram_5l01:auto_generated.q_a[2]
q_a[3] <= altsyncram_5l01:auto_generated.q_a[3]
q_a[4] <= altsyncram_5l01:auto_generated.q_a[4]
q_a[5] <= altsyncram_5l01:auto_generated.q_a[5]
q_a[6] <= altsyncram_5l01:auto_generated.q_a[6]
q_a[7] <= altsyncram_5l01:auto_generated.q_a[7]
q_a[8] <= altsyncram_5l01:auto_generated.q_a[8]
q_a[9] <= altsyncram_5l01:auto_generated.q_a[9]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|DDS|romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT