📄 prev_cmp_dds_project.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register reg1:u2\|q\[6\] register adder32:u3\|b\[31\] 329.38 MHz 3.036 ns Internal " "Info: Clock \"clk\" has Internal fmax of 329.38 MHz between source register \"reg1:u2\|q\[6\]\" and destination register \"adder32:u3\|b\[31\]\" (period= 3.036 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.812 ns + Longest register register " "Info: + Longest register to register delay is 2.812 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reg1:u2\|q\[6\] 1 REG LC_X12_Y10_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y10_N2; Fanout = 2; REG Node = 'reg1:u2\|q\[6\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reg1:u2|q[6] } "NODE_NAME" } } { "reg1.vhd" "" { Text "D:/FPGA/DDS_Project/reg1.vhd" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.993 ns) + CELL(0.326 ns) 1.319 ns adder32:u3\|b\[22\]~259COUT0 2 COMB LC_X11_Y8_N0 1 " "Info: 2: + IC(0.993 ns) + CELL(0.326 ns) = 1.319 ns; Loc. = LC_X11_Y8_N0; Fanout = 1; COMB Node = 'adder32:u3\|b\[22\]~259COUT0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.319 ns" { reg1:u2|q[6] adder32:u3|b[22]~259COUT0 } "NODE_NAME" } } { "adder32.vhd" "" { Text "D:/FPGA/DDS_Project/adder32.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 1.379 ns adder32:u3\|b\[22\]~256COUT0 3 COMB LC_X11_Y8_N1 1 " "Info: 3: + IC(0.000 ns) + CELL(0.060 ns) = 1.379 ns; Loc. = LC_X11_Y8_N1; Fanout = 1; COMB Node = 'adder32:u3\|b\[22\]~256COUT0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { adder32:u3|b[22]~259COUT0 adder32:u3|b[22]~256COUT0 } "NODE_NAME" } } { "adder32.vhd" "" { Text "D:/FPGA/DDS_Project/adder32.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 1.439 ns adder32:u3\|b\[22\]~253COUT0 4 COMB LC_X11_Y8_N2 1 " "Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 1.439 ns; Loc. = LC_X11_Y8_N2; Fanout = 1; COMB Node = 'adder32:u3\|b\[22\]~253COUT0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { adder32:u3|b[22]~256COUT0 adder32:u3|b[22]~253COUT0 } "NODE_NAME" } } { "adder32.vhd" "" { Text "D:/FPGA/DDS_Project/adder32.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 1.499 ns adder32:u3\|b\[22\]~250COUT0 5 COMB LC_X11_Y8_N3 1 " "Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 1.499 ns; Loc. = LC_X11_Y8_N3; Fanout = 1; COMB Node = 'adder32:u3\|b\[22\]~250COUT0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { adder32:u3|b[22]~253COUT0 adder32:u3|b[22]~250COUT0 } "NODE_NAME" } } { "adder32.vhd" "" { Text "D:/FPGA/DDS_Project/adder32.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.137 ns) 1.636 ns adder32:u3\|b\[22\]~247 6 COMB LC_X11_Y8_N4 1 " "Info: 6: + IC(0.000 ns) + CELL(0.137 ns) = 1.636 ns; Loc. = LC_X11_Y8_N4; Fanout = 1; COMB Node = 'adder32:u3\|b\[22\]~247'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.137 ns" { adder32:u3|b[22]~250COUT0 adder32:u3|b[22]~247 } "NODE_NAME" } } { "adder32.vhd" "" { Text "D:/FPGA/DDS_Project/adder32.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.160 ns) 1.796 ns adder32:u3\|b\[22\]~232 7 COMB LC_X11_Y8_N9 1 " "Info: 7: + IC(0.000 ns) + CELL(0.160 ns) = 1.796 ns; Loc. = LC_X11_Y8_N9; Fanout = 1; COMB Node = 'adder32:u3\|b\[22\]~232'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.160 ns" { adder32:u3|b[22]~247 adder32:u3|b[22]~232 } "NODE_NAME" } } { "adder32.vhd" "" { Text "D:/FPGA/DDS_Project/adder32.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 1.901 ns adder32:u3\|b\[22\]~217 8 COMB LC_X11_Y7_N4 5 " "Info: 8: + IC(0.000 ns) + CELL(0.105 ns) = 1.901 ns; Loc. = LC_X11_Y7_N4; Fanout = 5; COMB Node = 'adder32:u3\|b\[22\]~217'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.105 ns" { adder32:u3|b[22]~232 adder32:u3|b[22]~217 } "NODE_NAME" } } { "adder32.vhd" "" { Text "D:/FPGA/DDS_Project/adder32.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.160 ns) 2.061 ns adder32:u3\|b\[25\]~199 9 COMB LC_X11_Y7_N9 6 " "Info: 9: + IC(0.000 ns) + CELL(0.160 ns) = 2.061 ns; Loc. = LC_X11_Y7_N9; Fanout = 6; COMB Node = 'adder32:u3\|b\[25\]~199'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.160 ns" { adder32:u3|b[22]~217 adder32:u3|b[25]~199 } "NODE_NAME" } } { "adder32.vhd" "" { Text "D:/FPGA/DDS_Project/adder32.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 2.166 ns adder32:u3\|b\[30\]~209 10 COMB LC_X11_Y6_N4 1 " "Info: 10: + IC(0.000 ns) + CELL(0.105 ns) = 2.166 ns; Loc. = LC_X11_Y6_N4; Fanout = 1; COMB Node = 'adder32:u3\|b\[30\]~209'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.105 ns" { adder32:u3|b[25]~199 adder32:u3|b[30]~209 } "NODE_NAME" } } { "adder32.vhd" "" { Text "D:/FPGA/DDS_Project/adder32.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.646 ns) 2.812 ns adder32:u3\|b\[31\] 11 REG LC_X11_Y6_N5 1 " "Info: 11: + IC(0.000 ns) + CELL(0.646 ns) = 2.812 ns; Loc. = LC_X11_Y6_N5; Fanout = 1; REG Node = 'adder32:u3\|b\[31\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.646 ns" { adder32:u3|b[30]~209 adder32:u3|b[31] } "NODE_NAME" } } { "adder32.vhd" "" { Text "D:/FPGA/DDS_Project/adder32.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.819 ns ( 64.69 % ) " "Info: Total cell delay = 1.819 ns ( 64.69 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.993 ns ( 35.31 % ) " "Info: Total interconnect delay = 0.993 ns ( 35.31 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.812 ns" { reg1:u2|q[6] adder32:u3|b[22]~259COUT0 adder32:u3|b[22]~256COUT0 adder32:u3|b[22]~253COUT0 adder32:u3|b[22]~250COUT0 adder32:u3|b[22]~247 adder32:u3|b[22]~232 adder32:u3|b[22]~217 adder32:u3|b[25]~199 adder32:u3|b[30]~209 adder32:u3|b[31] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.812 ns" { reg1:u2|q[6] {} adder32:u3|b[22]~259COUT0 {} adder32:u3|b[22]~256COUT0 {} adder32:u3|b[22]~253COUT0 {} adder32:u3|b[22]~250COUT0 {} adder32:u3|b[22]~247 {} adder32:u3|b[22]~232 {} adder32:u3|b[22]~217 {} adder32:u3|b[25]~199 {} adder32:u3|b[30]~209 {} adder32:u3|b[31] {} } { 0.000ns 0.993ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.326ns 0.060ns 0.060ns 0.060ns 0.137ns 0.160ns 0.105ns 0.160ns 0.105ns 0.646ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.022 ns - Smallest " "Info: - Smallest clock skew is -0.022 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.107 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.107 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_17 114 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 114; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/FPGA/DDS_Project/dds.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.547 ns) 2.107 ns adder32:u3\|b\[31\] 2 REG LC_X11_Y6_N5 1 " "Info: 2: + IC(0.430 ns) + CELL(0.547 ns) = 2.107 ns; Loc. = LC_X11_Y6_N5; Fanout = 1; REG Node = 'adder32:u3\|b\[31\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.977 ns" { clk adder32:u3|b[31] } "NODE_NAME" } } { "adder32.vhd" "" { Text "D:/FPGA/DDS_Project/adder32.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 79.59 % ) " "Info: Total cell delay = 1.677 ns ( 79.59 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.430 ns ( 20.41 % ) " "Info: Total interconnect delay = 0.430 ns ( 20.41 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { clk adder32:u3|b[31] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.107 ns" { clk {} clk~out0 {} adder32:u3|b[31] {} } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.129 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.129 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_17 114 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 114; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/FPGA/DDS_Project/dds.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.547 ns) 2.129 ns reg1:u2\|q\[6\] 2 REG LC_X12_Y10_N2 2 " "Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X12_Y10_N2; Fanout = 2; REG Node = 'reg1:u2\|q\[6\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.999 ns" { clk reg1:u2|q[6] } "NODE_NAME" } } { "reg1.vhd" "" { Text "D:/FPGA/DDS_Project/reg1.vhd" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.77 % ) " "Info: Total cell delay = 1.677 ns ( 78.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.452 ns ( 21.23 % ) " "Info: Total interconnect delay = 0.452 ns ( 21.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk reg1:u2|q[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk {} clk~out0 {} reg1:u2|q[6] {} } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { clk adder32:u3|b[31] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.107 ns" { clk {} clk~out0 {} adder32:u3|b[31] {} } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk reg1:u2|q[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk {} clk~out0 {} reg1:u2|q[6] {} } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "reg1.vhd" "" { Text "D:/FPGA/DDS_Project/reg1.vhd" 25 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "adder32.vhd" "" { Text "D:/FPGA/DDS_Project/adder32.vhd" 30 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.812 ns" { reg1:u2|q[6] adder32:u3|b[22]~259COUT0 adder32:u3|b[22]~256COUT0 adder32:u3|b[22]~253COUT0 adder32:u3|b[22]~250COUT0 adder32:u3|b[22]~247 adder32:u3|b[22]~232 adder32:u3|b[22]~217 adder32:u3|b[25]~199 adder32:u3|b[30]~209 adder32:u3|b[31] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.812 ns" { reg1:u2|q[6] {} adder32:u3|b[22]~259COUT0 {} adder32:u3|b[22]~256COUT0 {} adder32:u3|b[22]~253COUT0 {} adder32:u3|b[22]~250COUT0 {} adder32:u3|b[22]~247 {} adder32:u3|b[22]~232 {} adder32:u3|b[22]~217 {} adder32:u3|b[25]~199 {} adder32:u3|b[30]~209 {} adder32:u3|b[31] {} } { 0.000ns 0.993ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.326ns 0.060ns 0.060ns 0.060ns 0.137ns 0.160ns 0.105ns 0.160ns 0.105ns 0.646ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { clk adder32:u3|b[31] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.107 ns" { clk {} clk~out0 {} adder32:u3|b[31] {} } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk reg1:u2|q[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk {} clk~out0 {} reg1:u2|q[6] {} } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "sum32:u1\|temp\[31\] freword\[6\] clk 5.966 ns register " "Info: tsu for register \"sum32:u1\|temp\[31\]\" (data pin = \"freword\[6\]\", clock pin = \"clk\") is 5.966 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.044 ns + Longest pin register " "Info: + Longest pin to register delay is 8.044 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns freword\[6\] 1 PIN PIN_100 3 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_100; Fanout = 3; PIN Node = 'freword\[6\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { freword[6] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/FPGA/DDS_Project/dds.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.987 ns) + CELL(0.434 ns) 6.551 ns sum32:u1\|temp\[6\]~1171 2 COMB LC_X12_Y8_N0 2 " "Info: 2: + IC(4.987 ns) + CELL(0.434 ns) = 6.551 ns; Loc. = LC_X12_Y8_N0; Fanout = 2; COMB Node = 'sum32:u1\|temp\[6\]~1171'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.421 ns" { freword[6] sum32:u1|temp[6]~1171 } "NODE_NAME" } } { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 6.611 ns sum32:u1\|temp\[7\]~1169 3 COMB LC_X12_Y8_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.060 ns) = 6.611 ns; Loc. = LC_X12_Y8_N1; Fanout = 2; COMB Node = 'sum32:u1\|temp\[7\]~1169'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { sum32:u1|temp[6]~1171 sum32:u1|temp[7]~1169 } "NODE_NAME" } } { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 6.671 ns sum32:u1\|temp\[8\]~1167 4 COMB LC_X12_Y8_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.060 ns) = 6.671 ns; Loc. = LC_X12_Y8_N2; Fanout = 2; COMB Node = 'sum32:u1\|temp\[8\]~1167'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { sum32:u1|temp[7]~1169 sum32:u1|temp[8]~1167 } "NODE_NAME" } } { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 6.731 ns sum32:u1\|temp\[9\]~1165 5 COMB LC_X12_Y8_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 6.731 ns; Loc. = LC_X12_Y8_N3; Fanout = 2; COMB Node = 'sum32:u1\|temp\[9\]~1165'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.060 ns" { sum32:u1|temp[8]~1167 sum32:u1|temp[9]~1165 } "NODE_NAME" } } { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.137 ns) 6.868 ns sum32:u1\|temp\[10\]~1163 6 COMB LC_X12_Y8_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.137 ns) = 6.868 ns; Loc. = LC_X12_Y8_N4; Fanout = 6; COMB Node = 'sum32:u1\|temp\[10\]~1163'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.137 ns" { sum32:u1|temp[9]~1165 sum32:u1|temp[10]~1163 } "NODE_NAME" } } { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.160 ns) 7.028 ns sum32:u1\|temp\[15\]~1153 7 COMB LC_X12_Y8_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.160 ns) = 7.028 ns; Loc. = LC_X12_Y8_N9; Fanout = 6; COMB Node = 'sum32:u1\|temp\[15\]~1153'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.160 ns" { sum32:u1|temp[10]~1163 sum32:u1|temp[15]~1153 } "NODE_NAME" } } { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 7.133 ns sum32:u1\|temp\[20\]~1143 8 COMB LC_X12_Y7_N4 6 " "Info: 8: + IC(0.000 ns) + CELL(0.105 ns) = 7.133 ns; Loc. = LC_X12_Y7_N4; Fanout = 6; COMB Node = 'sum32:u1\|temp\[20\]~1143'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.105 ns" { sum32:u1|temp[15]~1153 sum32:u1|temp[20]~1143 } "NODE_NAME" } } { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.160 ns) 7.293 ns sum32:u1\|temp\[25\]~1127 9 COMB LC_X12_Y7_N9 6 " "Info: 9: + IC(0.000 ns) + CELL(0.160 ns) = 7.293 ns; Loc. = LC_X12_Y7_N9; Fanout = 6; COMB Node = 'sum32:u1\|temp\[25\]~1127'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.160 ns" { sum32:u1|temp[20]~1143 sum32:u1|temp[25]~1127 } "NODE_NAME" } } { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.105 ns) 7.398 ns sum32:u1\|temp\[30\]~1137 10 COMB LC_X12_Y6_N4 1 " "Info: 10: + IC(0.000 ns) + CELL(0.105 ns) = 7.398 ns; Loc. = LC_X12_Y6_N4; Fanout = 1; COMB Node = 'sum32:u1\|temp\[30\]~1137'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.105 ns" { sum32:u1|temp[25]~1127 sum32:u1|temp[30]~1137 } "NODE_NAME" } } { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.646 ns) 8.044 ns sum32:u1\|temp\[31\] 11 REG LC_X12_Y6_N5 2 " "Info: 11: + IC(0.000 ns) + CELL(0.646 ns) = 8.044 ns; Loc. = LC_X12_Y6_N5; Fanout = 2; REG Node = 'sum32:u1\|temp\[31\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.646 ns" { sum32:u1|temp[30]~1137 sum32:u1|temp[31] } "NODE_NAME" } } { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.057 ns ( 38.00 % ) " "Info: Total cell delay = 3.057 ns ( 38.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.987 ns ( 62.00 % ) " "Info: Total interconnect delay = 4.987 ns ( 62.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.044 ns" { freword[6] sum32:u1|temp[6]~1171 sum32:u1|temp[7]~1169 sum32:u1|temp[8]~1167 sum32:u1|temp[9]~1165 sum32:u1|temp[10]~1163 sum32:u1|temp[15]~1153 sum32:u1|temp[20]~1143 sum32:u1|temp[25]~1127 sum32:u1|temp[30]~1137 sum32:u1|temp[31] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.044 ns" { freword[6] {} freword[6]~out0 {} sum32:u1|temp[6]~1171 {} sum32:u1|temp[7]~1169 {} sum32:u1|temp[8]~1167 {} sum32:u1|temp[9]~1165 {} sum32:u1|temp[10]~1163 {} sum32:u1|temp[15]~1153 {} sum32:u1|temp[20]~1143 {} sum32:u1|temp[25]~1127 {} sum32:u1|temp[30]~1137 {} sum32:u1|temp[31] {} } { 0.000ns 0.000ns 4.987ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.130ns 0.434ns 0.060ns 0.060ns 0.060ns 0.137ns 0.160ns 0.105ns 0.160ns 0.105ns 0.646ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 34 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.107 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.107 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_17 114 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 114; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/FPGA/DDS_Project/dds.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.547 ns) 2.107 ns sum32:u1\|temp\[31\] 2 REG LC_X12_Y6_N5 2 " "Info: 2: + IC(0.430 ns) + CELL(0.547 ns) = 2.107 ns; Loc. = LC_X12_Y6_N5; Fanout = 2; REG Node = 'sum32:u1\|temp\[31\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.977 ns" { clk sum32:u1|temp[31] } "NODE_NAME" } } { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 79.59 % ) " "Info: Total cell delay = 1.677 ns ( 79.59 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.430 ns ( 20.41 % ) " "Info: Total interconnect delay = 0.430 ns ( 20.41 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { clk sum32:u1|temp[31] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.107 ns" { clk {} clk~out0 {} sum32:u1|temp[31] {} } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.044 ns" { freword[6] sum32:u1|temp[6]~1171 sum32:u1|temp[7]~1169 sum32:u1|temp[8]~1167 sum32:u1|temp[9]~1165 sum32:u1|temp[10]~1163 sum32:u1|temp[15]~1153 sum32:u1|temp[20]~1143 sum32:u1|temp[25]~1127 sum32:u1|temp[30]~1137 sum32:u1|temp[31] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.044 ns" { freword[6] {} freword[6]~out0 {} sum32:u1|temp[6]~1171 {} sum32:u1|temp[7]~1169 {} sum32:u1|temp[8]~1167 {} sum32:u1|temp[9]~1165 {} sum32:u1|temp[10]~1163 {} sum32:u1|temp[15]~1153 {} sum32:u1|temp[20]~1143 {} sum32:u1|temp[25]~1127 {} sum32:u1|temp[30]~1137 {} sum32:u1|temp[31] {} } { 0.000ns 0.000ns 4.987ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.130ns 0.434ns 0.060ns 0.060ns 0.060ns 0.137ns 0.160ns 0.105ns 0.160ns 0.105ns 0.646ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { clk sum32:u1|temp[31] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.107 ns" { clk {} clk~out0 {} sum32:u1|temp[31] {} } { 0.000ns 0.000ns 0.430ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk da_data\[6\] romtab:u5\|lpm_rom:lpm_rom_component\|altrom:srom\|altsyncram:rom_block\|altsyncram_5l01:auto_generated\|ram_block1a4~porta_address_reg0 9.690 ns memory " "Info: tco from clock \"clk\" to destination pin \"da_data\[6\]\" through memory \"romtab:u5\|lpm_rom:lpm_rom_component\|altrom:srom\|altsyncram:rom_block\|altsyncram_5l01:auto_generated\|ram_block1a4~porta_address_reg0\" is 9.690 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.148 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 2.148 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_17 114 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 114; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/FPGA/DDS_Project/dds.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.556 ns) 2.148 ns romtab:u5\|lpm_rom:lpm_rom_component\|altrom:srom\|altsyncram:rom_block\|altsyncram_5l01:auto_generated\|ram_block1a4~porta_address_reg0 2 MEM M4K_X13_Y8 4 " "Info: 2: + IC(0.462 ns) + CELL(0.556 ns) = 2.148 ns; Loc. = M4K_X13_Y8; Fanout = 4; MEM Node = 'romtab:u5\|lpm_rom:lpm_rom_component\|altrom:srom\|altsyncram:rom_block\|altsyncram_5l01:auto_generated\|ram_block1a4~porta_address_reg0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.018 ns" { clk romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|ram_block1a4~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_5l01.tdf" "" { Text "D:/FPGA/DDS_Project/db/altsyncram_5l01.tdf" 110 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.686 ns ( 78.49 % ) " "Info: Total cell delay = 1.686 ns ( 78.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.462 ns ( 21.51 % ) " "Info: Total interconnect delay = 0.462 ns ( 21.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.148 ns" { clk romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|ram_block1a4~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.148 ns" { clk {} clk~out0 {} romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|ram_block1a4~porta_address_reg0 {} } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.556ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" { } { { "db/altsyncram_5l01.tdf" "" { Text "D:/FPGA/DDS_Project/db/altsyncram_5l01.tdf" 110 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.042 ns + Longest memory pin " "Info: + Longest memory to pin delay is 7.042 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns romtab:u5\|lpm_rom:lpm_rom_component\|altrom:srom\|altsyncram:rom_block\|altsyncram_5l01:auto_generated\|ram_block1a4~porta_address_reg0 1 MEM M4K_X13_Y8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y8; Fanout = 4; MEM Node = 'romtab:u5\|lpm_rom:lpm_rom_component\|altrom:srom\|altsyncram:rom_block\|altsyncram_5l01:auto_generated\|ram_block1a4~porta_address_reg0'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|ram_block1a4~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_5l01.tdf" "" { Text "D:/FPGA/DDS_Project/db/altsyncram_5l01.tdf" 110 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.314 ns) 3.314 ns romtab:u5\|lpm_rom:lpm_rom_component\|altrom:srom\|altsyncram:rom_block\|altsyncram_5l01:auto_generated\|q_a\[6\] 2 MEM M4K_X13_Y8 1 " "Info: 2: + IC(0.000 ns) + CELL(3.314 ns) = 3.314 ns; Loc. = M4K_X13_Y8; Fanout = 1; MEM Node = 'romtab:u5\|lpm_rom:lpm_rom_component\|altrom:srom\|altsyncram:rom_block\|altsyncram_5l01:auto_generated\|q_a\[6\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.314 ns" { romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|ram_block1a4~porta_address_reg0 romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|q_a[6] } "NODE_NAME" } } { "db/altsyncram_5l01.tdf" "" { Text "D:/FPGA/DDS_Project/db/altsyncram_5l01.tdf" 31 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.094 ns) + CELL(1.634 ns) 7.042 ns da_data\[6\] 3 PIN PIN_85 0 " "Info: 3: + IC(2.094 ns) + CELL(1.634 ns) = 7.042 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'da_data\[6\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.728 ns" { romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|q_a[6] da_data[6] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/FPGA/DDS_Project/dds.vhd" 24 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.948 ns ( 70.26 % ) " "Info: Total cell delay = 4.948 ns ( 70.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.094 ns ( 29.74 % ) " "Info: Total interconnect delay = 2.094 ns ( 29.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.042 ns" { romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|ram_block1a4~porta_address_reg0 romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|q_a[6] da_data[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.042 ns" { romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|ram_block1a4~porta_address_reg0 {} romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|q_a[6] {} da_data[6] {} } { 0.000ns 0.000ns 2.094ns } { 0.000ns 3.314ns 1.634ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.148 ns" { clk romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|ram_block1a4~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.148 ns" { clk {} clk~out0 {} romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|ram_block1a4~porta_address_reg0 {} } { 0.000ns 0.000ns 0.462ns } { 0.000ns 1.130ns 0.556ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.042 ns" { romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|ram_block1a4~porta_address_reg0 romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|q_a[6] da_data[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.042 ns" { romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|ram_block1a4~porta_address_reg0 {} romtab:u5|lpm_rom:lpm_rom_component|altrom:srom|altsyncram:rom_block|altsyncram_5l01:auto_generated|q_a[6] {} da_data[6] {} } { 0.000ns 0.000ns 2.094ns } { 0.000ns 3.314ns 1.634ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "sum32:u1\|temp\[2\] freword\[2\] clk -3.633 ns register " "Info: th for register \"sum32:u1\|temp\[2\]\" (data pin = \"freword\[2\]\", clock pin = \"clk\") is -3.633 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.129 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.129 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_17 114 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_17; Fanout = 114; CLK Node = 'clk'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/FPGA/DDS_Project/dds.vhd" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.547 ns) 2.129 ns sum32:u1\|temp\[2\] 2 REG LC_X12_Y9_N6 4 " "Info: 2: + IC(0.452 ns) + CELL(0.547 ns) = 2.129 ns; Loc. = LC_X12_Y9_N6; Fanout = 4; REG Node = 'sum32:u1\|temp\[2\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.999 ns" { clk sum32:u1|temp[2] } "NODE_NAME" } } { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 78.77 % ) " "Info: Total cell delay = 1.677 ns ( 78.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.452 ns ( 21.23 % ) " "Info: Total interconnect delay = 0.452 ns ( 21.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk sum32:u1|temp[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk {} clk~out0 {} sum32:u1|temp[2] {} } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" { } { { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 34 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.774 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.774 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns freword\[2\] 1 PIN PIN_129 3 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_129; Fanout = 3; PIN Node = 'freword\[2\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { freword[2] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/FPGA/DDS_Project/dds.vhd" 20 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.172 ns) + CELL(0.467 ns) 5.774 ns sum32:u1\|temp\[2\] 2 REG LC_X12_Y9_N6 4 " "Info: 2: + IC(4.172 ns) + CELL(0.467 ns) = 5.774 ns; Loc. = LC_X12_Y9_N6; Fanout = 4; REG Node = 'sum32:u1\|temp\[2\]'" { } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.639 ns" { freword[2] sum32:u1|temp[2] } "NODE_NAME" } } { "sum32.vhd" "" { Text "D:/FPGA/DDS_Project/sum32.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.602 ns ( 27.75 % ) " "Info: Total cell delay = 1.602 ns ( 27.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.172 ns ( 72.25 % ) " "Info: Total interconnect delay = 4.172 ns ( 72.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.774 ns" { freword[2] sum32:u1|temp[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.774 ns" { freword[2] {} freword[2]~out0 {} sum32:u1|temp[2] {} } { 0.000ns 0.000ns 4.172ns } { 0.000ns 1.135ns 0.467ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.129 ns" { clk sum32:u1|temp[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.129 ns" { clk {} clk~out0 {} sum32:u1|temp[2] {} } { 0.000ns 0.000ns 0.452ns } { 0.000ns 1.130ns 0.547ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.774 ns" { freword[2] sum32:u1|temp[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.774 ns" { freword[2] {} freword[2]~out0 {} sum32:u1|temp[2] {} } { 0.000ns 0.000ns 4.172ns } { 0.000ns 1.135ns 0.467ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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