reg2.vhd.bak

频率计 等精度频率计 可以用于频率测试的等精度频率计 可用的

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-- Project Name：  DDS_Project
-- File Name：	   reg2.vhd
-- Create Date:    19:55:10 2008-05-09
-- Engineer:	   Kun Yue
-- Target Device:  
-- Tool versions:  QuartusII 7.2
-- Description:    寄存器2
-- Additional Comments:   	
--			   	d[31..0]----输入信号	q[31..0]----输出信号			
--				clk----时钟信号				
-- Revision: V1.0
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library ieee;
use ieee.std_logic_1164.all;
entity reg2 is
   port(e: in std_logic_vector(31 downto 0);
        clk:in std_logic;
        p:out std_logic_vector(31 downto 0));
end entity reg2;
architecture art  of reg2 is
  begin
 process(clk) is
  begin 
 if clk'event and clk='1'then
   p<=e;
 end if;
 end process;
end architecture art;