romtab.vhd

频率计 等精度频率计 可以用于频率测试的等精度频率计 可用的

--------------------------------------------------------------------------------
-- Project Name：  DDS_Project
-- File Name：	   dds.vhd
-- Create Date:    20:20:15 2008-05-09
-- Engineer:	   Kun Yue
-- Target Device:  
-- Tool versions:  QuartusII 7.2
-- Description:    DDS顶层文件
-- Additional Comments:   	
--						k[31..0]----输入信号		en----使能信号		
--			      		reset----复位信号		out1[31..0]----输出信号		
--			      		clk----时钟信号
-- Revision: V1.0
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library lpm;
use lpm.lpm_components.all;

entity romtab is
       port(
             inclock         : in  std_logic;
             phase_address   : in  std_logic_vector (9 downto 0);--phase address value
             q : out std_logic_vector (9 downto 0)--wave sin value
            );
end romtab;

architecture arc_rom of romtab is

    signal sub_wire0	: std_logic_vector (9 downto 0);
------------------------------------------------------------------------------	
	component lpm_rom                      --sin wave rom
	generic (
		lpm_width		     : positive;
		lpm_widthad		     : positive;
		lpm_address_control  : string;
		lpm_indata		     : string;
		lpm_outdata		     : string;
		lpm_file		     : string
	);
	port (
			address	: in  std_logic_vector (9 downto 0);
			inclock	: in  std_logic ;
			q	: out std_logic_vector (9 downto 0)
	);
	end component;
begin	
	q <= sub_wire0(9 downto 0);

	lpm_rom_component : lpm_rom
	generic map (
		lpm_width => 10,
		lpm_widthad => 10,
		lpm_address_control => "registered",
		lpm_indata => "registered",
		lpm_outdata => "unregistered",
		lpm_file => "./data/sin_rom.mif"
	)
	port map (address => phase_address,inclock => inclock,q => sub_wire0);	
end arc_rom;