📄 mainstoneii.h
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//Interrupt Pending Control Register 2 (Read/Write)
typedef struct
{
UINT8 IPCR2;
} CPLD_IPCR2_REGS, *P_CPLD_IPCR2_REGS;
*/
#define nSYNC_UART_INT_PENDING (1<<7) //0=normal, 1=active
#define nSYNC_UART_DCD_PENDING (1<<6) //0=normal, 1=active
#define nSYNC_UART_RI_PENDING (1<<5) //0=normal, 1=active
#define nSCANNER_INT_PENDING (1<<4) //0=normal, 1=active
#define nSCANNER_POWER_PENDING (1<<3) //0=normal, 1=active (in power down mode)
#define nGSM_UART1_INT_PENDING (1<<2) //0=normal, 1=active
#define nGSM_UART2_INT_PENDING (1<<1) //0=normal, 1=active
#define nGSM_MODULE_RI_PENDING (1<<0) //0=normal, 1=active
#define nIPCR2_MASK (0xFF)
/*
//Interrupt Pending Control Register 3 (Read/Write)
typedef struct
{
UINT8 IPCR3;
} CPLD_IPCR3_REGS, *P_CPLD_IPCR3_REGS;
*/
#define nMICROP_INT_PENDING (1<<7) //0=normal, 1=active
#define nTRIGGER_SW1_PENDING (1<<6) //0=normal, 1=active
#define nTRIGGER_SW2_PENDING (1<<5) //0=normal, 1=active
#define nFINGER_INT_PENDING (1<<4) //0=normal, 1=active
#define nKEYPAD_INT_PENDING (1<<3) //0=normal, 1=active
#define nRFID_INT_PENDING (1<<2) //0=normal, 1=active
#define nDEBUG_LAN_INT_PENDING (1<<1) //0=normal, 1=active
#define nGPS_UART_INT_PENDING (1<<0) //0=normal, 1=active
#define nIPCR3_MASK (0xFF)
/*
//Interrupt Enable Control Register 1 (Write Only)
typedef struct
{
UINT8 IECR1;
} CPLD_IECR1_REGS, *P_CPLD_IECR1_REGS;
*/
#define nCF_SLOT0_IRQ_ENABLE (1<<7) //0=disable, 1=enable
#define nCF_SLOT0_STSCHG_ENABLE (1<<6) //0=disable, 1=enable
#define nCF_SLOT1_IRQ_ENABLE (1<<5) //0=disable, 1=enable
#define nCF_SLOT1_STSCHG_ENABLE (1<<4) //0=disable, 1=enable
#define nHEADSET_DETECT_ENABLE (1<<3) //0=disable, 1=enable
#define nUSB_DETECT_ENABLE (1<<2) //0=disable, 1=enable
#define nREAD_GOOD_2D_ENABLE (1<<1) //0=disable, 1=enable
#define nDEBUG_IN_ENABLE (1<<0) //0=disable, 1=enable
#define nIECR1_MASK (0xFF)
/*
//Interrupt Enable Control Register 2 (Write Only)
typedef struct
{
UINT8 IECR2;
} CPLD_IECR2_REGS, *P_CPLD_IECR2_REGS;
*/
#define nSYNC_UART_INT_ENABLE (1<<7) //0=disable, 1=enable
#define nSYNC_UART_DCD_ENABLE (1<<6) //0=disable, 1=enable
#define nSYNC_UART_RI_ENABLE (1<<5) //0=disable, 1=enable
#define nSCANNER_INT_ENABLE (1<<4) //0=disable, 1=enable
#define nSCANNER_POWER_ENABLE (1<<3) //0=disable, 1=enable (in power down mode)
#define nGSM_UART1_INT_ENABLE (1<<2) //0=disable, 1=enable
#define nGSM_UART2_INT_ENABLE (1<<1) //0=disable, 1=enable
#define nGSM_MODULE_RI_ENABLE (1<<0) //0=disable, 1=enable
#define nIECR2_MASK (0xFF)
/*
//Interrupt Enable Control Register 3 (Write Only)
typedef struct
{
UINT8 IECR3;
} CPLD_IECR3_REGS, *P_CPLD_IECR3_REGS;
*/
#define nMICROP_INT_ENABLE (1<<7) //0=disable, 1=enable
#define nTRIGGER_SW1_ENABLE (1<<6) //0=disable, 1=enable
#define nTRIGGER_SW2_ENABLE (1<<5) //0=disable, 1=enable
#define nFINGER_INT_ENABLE (1<<4) //0=disable, 1=enable
#define nKEYPAD_INT_ENABLE (1<<3) //0=disable, 1=enable
#define nRFID_INT_ENABLE (1<<2) //0=disable, 1=enable
#define nDEBUG_LAN_INT_ENABLE (1<<1) //0=disable, 1=enable
#define nGPS_UART_INT_ENABLE (1<<0) //0=disable, 1=enable
#define nIECR3_MASK (0xFF)
/*
//Interrupt Wakeup Enable Control Register 1 (Write Only)
typedef struct
{
UINT8 IWECR1;
} CPLD_IWECR1_REGS, *P_CPLD_IWECR1_REGS;
*/
#define nCF_SLOT0_IRQ_WAKEUP_ENABLE (1<<7) //0=disable, 1=enable
#define nCF_SLOT0_STSCHG_WAKEUP_ENABLE (1<<6) //0=disable, 1=enable
#define nCF_SLOT1_IRQ_WAKEUP_ENABLE (1<<5) //0=disable, 1=enable
#define nCF_SLOT1_STSCHG_WAKEUP_ENABLE (1<<4) //0=disable, 1=enable
#define nHEADSET_DETECT_WAKEUP_ENABLE (1<<3) //0=disable, 1=enable
#define nUSB_DETECT_WAKEUP_ENABLE (1<<2) //0=disable, 1=enable
#define nREAD_GOOD_2D_WAKEUP_ENABLE (1<<1) //0=disable, 1=enable
#define nDEBUG_IN_WAKEUP_ENABLE (1<<0) //0=disable, 1=enable
/*
//Interrupt Wakeup Enable Control Register 2 (Write Only)
typedef struct
{
UINT8 IWECR2;
} CPLD_IWECR2_REGS, *P_CPLD_IWECR2_REGS;
*/
#define nSYNC_UART_INT_WAKEUP_ENABLE (1<<7) //0=disable, 1=enable
#define nSYNC_UART_DCD_WAKEUP_ENABLE (1<<6) //0=disable, 1=enable
#define nSYNC_UART_RI_WAKEUP_ENABLE (1<<5) //0=disable, 1=enable
#define nSCANNER_INT_WAKEUP_ENABLE (1<<4) //0=disable, 1=enable
#define nSCANNER_POWER_WAKEUP_ENABLE (1<<3) //0=disable, 1=enable (in power down mode)
#define nGSM_UART1_INT_WAKEUP_ENABLE (1<<2) //0=disable, 1=enable
#define nGSM_UART2_INT_WAKEUP_ENABLE (1<<1) //0=disable, 1=enable
#define nGSM_MODULE_RI_WAKEUP_ENABLE (1<<0) //0=disable, 1=enable
/*
//Interrupt Wakeup Enable Control Register 3 (Write Only)
typedef struct
{
UINT8 IWECR3;
} CPLD_IWECR3_REGS, *P_CPLD_IWECR3_REGS;
*/
#define nMICROP_INT_WAKEUP_ENABLE (1<<7) //0=disable, 1=enable
#define nTRIGGER_SW1_WAKEUP_ENABLE (1<<6) //0=disable, 1=enable
#define nTRIGGER_SW2_WAKEUP_ENABLE (1<<5) //0=disable, 1=enable
#define nFINGER_INT_WAKEUP_ENABLE (1<<4) //0=disable, 1=enable
#define nKEYPAD_INT_WAKEUP_ENABLE (1<<3) //0=disable, 1=enable
#define nRFID_INT_WAKEUP_ENABLE (1<<2) //0=disable, 1=enable
#define nDEBUG_LAN_INT_WAKEUP_ENABLE (1<<1) //0=disable, 1=enable
#define nGPS_UART_INT_WAKEUP_ENABLE (1<<0) //0=disable, 1=enable
//Hudson[NP2005-051205-Start]
//Declare for CPLD library function.
#define NOMASK 0x00
#define INPOWERHANDLER TRUE
#define NOTINPOWERHANDLER FALSE
//Hudson[NP2005-051205-End]
//Hudson[CP-040605-End]
//Hudson[NP2005-052605-Start]
//NP2005 wakeup sources
#define POWER_BUTTON_WAKEUP 0x00000001
#define CPLD_CF_SLOT0_IRQ_WAKEUP 0x00000002
#define CF_SLOT0_STSCHG_WAKEUP 0x00000004
#define CF_SLOT1_IRQ_WAKEUP 0x00000008
#define CF_SLOT1_STSCHG_WAKEUP 0x00000010
#define HEADSET_DETECT_WAKEUP 0x00000020
#define USB_DETECT_WAKEUP 0x00000040
#define READ_GOOD_2D_WAKEUP 0x00000080
#define DEBUG_IN_WAKEUP 0x00000100
#define SYNC_UART_INT_WAKEUP 0x00000200
#define SYNC_UART_DCD_WAKEUP 0x00000400
#define SYNC_UART_RI_WAKEUP 0x00000800
#define SCANNER_INT_WAKEUP 0x00001000
#define SCANNER_POWER_WAKEUP 0x00002000
#define GSM_UART1_INT_WAKEUP 0x00004000
#define GSM_UART2_INT_WAKEUP 0x00008000
#define GSM_MODULE_RI_WAKEUP 0x00010000
#define MICROP_INT_WAKEUP 0x00020000
#define TRIGGER_SW1_WAKEUP 0x00040000
#define TRIGGER_SW2_WAKEUP 0x00080000
#define FINGER_INT_WAKEUP 0x00100000
#define KEYPAD_INT_WAKEUP 0x00200000
#define RFID_INT_WAKEUP 0x00400000
#define DEBUG_LAN_INT_WAKEUP 0x00800000
#define GPS_UART_INT_WAKEUP 0x01000000
//Hudson[NP2005-052605-End]
//
// CorePlatform: CS2 External I/O CPLD Registers
//
/*
typedef struct
{
UINT32 rsvd0[0x64]; // 0800_0000 -> 0800_00FF
UINT32 rsvd1[0x64]; // 0800_0100 -> 0800_01FF
UINT32 rsvd2[0x64]; // 0800_0200 -> 0800_02FF
UINT32 rsvd3[0x64]; // 0800_0300 -> 0800_03FF
UINT32 rsvd4[0x64]; // 0800_0400 -> 0800_04FF
UINT32 rsvd5[0x64]; // 0800_0500 -> 0800_05FF
UINT32 rsvd6[0x64]; // 0800_0600 -> 0800_06FF
UINT32 rsvd7[0x64]; // 0800_0700 -> 0080_07FF
UINT8 CPLDVersion; // 0800_0800
UINT8 rsvd8[3]; // 0800_0801 -> 0080_0803
UINT32 rsvd9[0x63]; // 0800_0804 -> 0080_08FF
UINT8 DCR1; // 0800_0900
UINT8 rsvd10[3]; // 0800_0901 -> 0080_0903
UINT32 rsvd11[0x63]; // 0800_0904 -> 0080_09FF
UINT8 DCR2; // 0800_0A00
UINT8 rsvd12[3]; // 0800_0A01 -> 0080_0A03
UINT32 rsvd13[0x63]; // 0800_0A04 -> 0080_0AFF
UINT8 DCR3; // 0800_0B00
UINT8 rsvd14[3]; // 0800_0B01 -> 0080_0B03
UINT32 rsvd15[0x63]; // 0800_0B04 -> 0080_0BFF
UINT8 DCR4; // 0800_0C00
UINT8 rsvd16[3]; // 0800_0C01 -> 0080_0C03
UINT32 rsvd17[0x63]; // 0800_0C04 -> 0080_0CFF
UINT8 DRCR1; // 0800_0D00
UINT8 rsvd18[3]; // 0800_0D01 -> 0080_0D03
UINT32 rsvd19[0x63]; // 0800_0D04 -> 0080_0DFF
UINT8 DRCR2; // 0800_0E00
UINT8 rsvd20[3]; // 0800_0E01 -> 0080_0E03
UINT32 rsvd21[0x63]; // 0800_0E04 -> 0080_0EFF
UINT8 KPSSKR; // 0800_0F00
UINT8 rsvd22[3]; // 0800_0F01 -> 0080_0F03
UINT32 rsvd23[0x63]; // 0800_0F04 -> 0080_0FFF
UINT8 MKC0; // 0800_1000
UINT8 rsvd24[3]; // 0800_1001 -> 0080_1003
UINT32 rsvd25[0x63]; // 0800_1004 -> 0080_10FF
UINT8 MKC1; // 0800_1100
UINT8 rsvd26[3]; // 0800_1101 -> 0080_1103
UINT32 rsvd27[0x63]; // 0800_1104 -> 0080_11FF
UINT8 MKC2; // 0800_1200
UINT8 rsvd28[3]; // 0800_1201 -> 0080_1203
UINT32 rsvd29[0x63]; // 0800_1204 -> 0080_12FF
UINT8 MKC3; // 0800_1300
UINT8 rsvd30[3]; // 0800_1301 -> 0080_1303
UINT32 rsvd31[0x63]; // 0800_1304 -> 0080_13FF
UINT8 MKC4; // 0800_1400
UINT8 rsvd32[3]; // 0800_1401 -> 0080_1403
UINT32 rsvd33[0x63]; // 0800_1404 -> 0080_14FF
UINT8 MKC5; // 0800_1500
UINT8 rsvd34[3]; // 0800_1501 -> 0080_1503
UINT32 rsvd35[0x63]; // 0800_1504 -> 0080_15FF
UINT8 MKC6; // 0800_1600
UINT8 rsvd36[3]; // 0800_1601 -> 0080_1603
UINT32 rsvd37[0x63]; // 0800_1604 -> 0080_16FF
UINT8 MKC7; // 0800_1700
UINT8 rsvd38[3]; // 0800_1701 -> 0080_1703
UINT32 rsvd39[0x63]; // 0800_1704 -> 0080_17FF
UINT8 KLCR; // 0800_1800
UINT8 rsvd40[3]; // 0800_1801 -> 0080_1803
UINT32 rsvd41[0x63]; // 0800_1804 -> 0080_18FF
UINT8 KR0_WKER; // 0800_1900
UINT8 rsvd42[3]; // 0800_1901 -> 0080_1903
UINT32 rsvd43[0x63]; // 0800_1904 -> 0080_19FF
UINT8 KR1_WKER; // 0800_1A00
UINT8 rsvd44[3]; // 0800_1A01 -> 0080_1A03
UINT32 rsvd45[0x63]; // 0800_1A04 -> 0080_1AFF
UINT8 KIDS; // 0800_1B00
UINT8 rsvd46[3]; // 0800_1B01 -> 0080_1B03
UINT32 rsvd47[0x63]; // 0800_1B04 -> 0080_1BFF
UINT8 ISCR1; // 0800_1C00
UINT8 rsvd48[3]; // 0800_1C01 -> 0080_1C03
UINT32 rsvd49[0x63]; // 0800_1C04 -> 0080_1CFF
UINT8 ISCR2; // 0800_1D00
UINT8 rsvd50[3]; // 0800_1D01 -> 0080_1D03
UINT32 rsvd51[0x63]; // 0800_1D04 -> 0080_1DFF
UINT8 ISCR3; // 0800_1E00
UINT8 rsvd52[3]; // 0800_1E01 -> 0080_1E03
UINT32 rsvd53[0x63]; // 0800_1E04 -> 0080_1EFF
UINT8 IPCR1; // 0800_1F00
UINT8 rsvd54[3]; // 0800_1F01 -> 0080_1F03
UINT32 rsvd55[0x63]; // 0800_1F04 -> 0080_1FFF
UINT8 IPCR2; // 0800_2000
UINT8 rsvd56[3]; // 0800_2001 -> 0080_2003
UINT32 rsvd57[0x63]; // 0800_2004 -> 0080_20FF
UINT8 IPCR3; // 0800_2100
UINT8 rsvd58[3]; // 0800_2101 -> 0080_2103
UINT32 rsvd59[0x63]; // 0800_2104 -> 0080_21FF
UINT8 IECR1; // 0800_2200
UINT8 rsvd60[3]; // 0800_2201 -> 0080_2203
UINT32 rsvd61[0x63]; // 0800_2204 -> 0080_22FF
UINT8 IECR2; // 0800_2300
UINT8 rsvd62[3]; // 0800_2301 -> 0080_2303
UINT32 rsvd63[0x63]; // 0800_2304 -> 0080_23FF
UINT8 IECR3; // 0800_2400
UINT8 rsvd64[3]; // 0800_2401 -> 0080_2403
UINT32 rsvd65[0x63]; // 0800_2404 -> 0080_24FF
UINT8 IWECR1; // 0800_2500
UINT8 rsvd66[3]; // 0800_2501 -> 0080_2503
UINT32 rsvd67[0x63]; // 0800_2504 -> 0080_25FF
UINT8 IWECR2; // 0800_2600
UINT8 rsvd68[3]; // 0800_2601 -> 0080_2603
UINT32 rsvd69[0x63]; // 0800_2604 -> 0080_26FF
UINT8 IWECR3; // 0800_2700
UINT8 rsvd70[3]; // 0800_2701 -> 0080_2703
UINT32 rsvd71[0x63]; // 0800_2704 -> 0080_27FF
} COREPLATFORM_CPLD_REGS, *PCOREPLATFORM_CPLD_REGS;
*/
/////////////////////////////////////////////////////////////////////////////////////////
/* PERIPHERAL OFFSETS */
/////////////////////////////////////////////////////////////////////////////////////////
#define DMAC_OFFSET 0x0 // DMA CONTROLLER
#define FFUART_OFFSET 0x00100000 // Full-Feature UART
#define BTUART_OFFSET 0x00200000 // BlueTooth UART
#define I2C_OFFSET 0x00300000 // I2C
#define I2S_OFFSET 0x00400000 // I2S
#define AC97_OFFSET 0x00500000 // AC97
#define UDC_OFFSET 0x00600000 // UDC (usb client)
#define STUART_OFFSET 0x00700000 // Standard UART
#define FIR_OFFSET 0x00800000 // FIR
#define RTC_OFFSET 0x00900000 // real time clock
#define OST_OFFSET 0x00A00000 // OS Timer
#define PWM0_2_OFFSET 0x00B00000 // PWM 0 (pulse-width mod)
#define PWM1_3_OFFSET 0x00C00000 // PWM 1 (pulse-width mod)
#define INTC_OFFSET 0x00D00000 // Interrupt controller
#define GPIO_OFFSET 0x00E00000 // GPIO
#define PWR_OFFSET 0x00F00000 // Power Manager and Reset Control
#define SSP1_OFFSET 0x01000000 // SSP 1
#define MMC_OFFSET 0x01100000 // MMC
#define CLK_OFFSET 0x01300000 // Clock Manager
#define BB_OFFSET 0x01400000 // Baseband Interface
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