📄 mainstoneii.h
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
// File: mainstoneii.h
//
// This header file contains Mainstone II specific definitions.
//
#ifndef __MAINSTONEII_H__
#define __MAINSTONEII_H__
//
// MEMC
//
typedef struct
{
volatile unsigned long mdcnfg;
volatile unsigned long mdrefr;
volatile unsigned long msc0;
volatile unsigned long msc1;
volatile unsigned long msc2;
volatile unsigned long mecr;
volatile unsigned long rsvd0;
volatile unsigned long sxcnfg;
volatile unsigned long flycnfg;
volatile unsigned long rsvd1;
volatile unsigned long mcmem0;
volatile unsigned long mcmem1;
volatile unsigned long mcatt0;
volatile unsigned long mcatt1;
volatile unsigned long mcio0;
volatile unsigned long mcio1;
volatile unsigned long mdmrs;
volatile unsigned long boot_def;
volatile unsigned long arb_cntl;
volatile unsigned long bscntrp;
volatile unsigned long bscntrn;
volatile unsigned long lcdbscntr;
volatile unsigned long mdmrslp;
} MEMC_STRUCT, *PMEMC;
/////////////////////////////////////////////////////////////////////////////////////////
// CORE PLATFORM External I/O (CPLD) Registers
//
//
// CorePlatform: nCS2: External I/O DEVICES (8MB)
// Include SCANNER, GSM UART1, GSM UART2, UART ACTIVE SYNC, GPS, DEBUG UART, DEBUG LAN and RFID
//
#define COREPLATFORM_BASE_REG_PA_EXTIO_DEVICES 0x08000000
//Hudson[NP2005-051305-Start]
//Declare external I/O device physical address.
#define CS6_SCANNER_OFFSET 0x00000000
#define CS7_GSMUART1_OFFSET 0x00100000
#define CS8_GSMUART2_OFFSET 0x00200000
#define CS9_SYNCUART_OFFSET 0x00300000
#define CS10_GPS_OFFSET 0x00400000
#define CS11_DEBUGUART_OFFSET 0x00500000
#define CS12_DEBUGLAN_OFFSET 0x00600000
#define CS13_RFID_OFFSET 0x00700000
#define EXTIO_BASE_REG_PA_SCANNER COREPLATFORM_BASE_REG_PA_EXTIO_DEVICES+CS6_SCANNER_OFFSET
#define EXTIO_BASE_REG_PA_GSMUART1 COREPLATFORM_BASE_REG_PA_EXTIO_DEVICES+CS7_GSMUART1_OFFSET
#define EXTIO_BASE_REG_PA_GSMUART2 COREPLATFORM_BASE_REG_PA_EXTIO_DEVICES+CS8_GSMUART2_OFFSET
#define EXTIO_BASE_REG_PA_SYNCUART COREPLATFORM_BASE_REG_PA_EXTIO_DEVICES+CS9_SYNCUART_OFFSET
#define EXTIO_BASE_REG_PA_GPS COREPLATFORM_BASE_REG_PA_EXTIO_DEVICES+CS10_GPS_OFFSET
#define EXTIO_BASE_REG_PA_DEBUGUART COREPLATFORM_BASE_REG_PA_EXTIO_DEVICES+CS11_DEBUGUART_OFFSET
#define EXTIO_BASE_REG_PA_DEBUGLAN COREPLATFORM_BASE_REG_PA_EXTIO_DEVICES+CS12_DEBUGLAN_OFFSET
#define EXTIO_BASE_REG_PA_RFID COREPLATFORM_BASE_REG_PA_EXTIO_DEVICES+CS13_RFID_OFFSET
//------------------------------------------------------------------------------
//
// Type: TL16C550DI_UART_REG
//
// SYNC UART control registers.
//
typedef struct {
unsigned long thr_rbr_dll; // DLAB = 0 WO 8bit - Transmit Holding Register (THR).
// DLAB = 0 RO 8bit - Receive Buffer Register (RBR).
// DLAB = 1 RW 8bit - Divisor Latch Low Register (DLL).
unsigned long ier_dlh; // DLAB = 0 RW 8bit - Interrupt Enable Register.
unsigned long iir_fcr; // DLAB = X RO 8bit - Interrupt Identification Register.
unsigned long lcr; // DLAB = X RW 8bit - Line Control Register.
unsigned long mcr; // DLAB = X RW 8bit - Modem Control Regiser.
unsigned long lsr; // DLAB = X RO 8bit - Line Status Register.
unsigned long msr; // DLAB = X RO 8bit - Modem Status Register.
unsigned long scr; // DLAB = X RW 8bit - Scratchpad Register.
} TL16C550DI_UART_REG, *PTL16C550DI_UART_REG;
//Hudson[NP2005-051305-End]
//
// CorePlatform: nCS2: External I/O CPLD (32 MB)
//
#define COREPLATFORM_BASE_REG_PA_CPLD 0x09000000
#define VER_OFFSET 0x00000000 //CPLD Version
#define DCR1_OFFSET 0x00100000 //Device Control Register 1
#define DCR2_OFFSET 0x00200000 //Device Control Register 2
#define DCR3_OFFSET 0x00300000 //Device Control Register 3
#define DCR4_OFFSET 0x00400000 //Device Control Register 4
#define DRCR1_OFFSET 0x00500000 //Device Reset Control Register 1
#define DRCR2_OFFSET 0x00600000 //Device Reset Control Register 2
#define KPSSKR_OFFSET 0x00700000 //Keypad Pressing Status and Single Key Register
#define MKC0_CR_OFFSET 0x00800000 //Multi Key Column 0 Control Register
#define MKC1_CR_OFFSET 0x00900000 //Multi Key Column 1 Control Register
#define MKC2_CR_OFFSET 0x00A00000 //Multi Key Column 2 Control Register
#define MKC3_CR_OFFSET 0x00B00000 //Multi Key Column 3 Control Register
#define MKC4_CR_OFFSET 0x00C00000 //Multi Key Column 4 Control Register
#define MKC5_CR_OFFSET 0x00D00000 //Multi Key Column 5 Control Register
#define MKC6_CR_OFFSET 0x00E00000 //Multi Key Column 6 Contrpl Register
#define MKC7_CR_OFFSET 0x00F00000 //Multi Key Column 7 Control Register
#define KLCR_OFFSET 0x01000000 //Keypad LED Control Register
#define KR0_WKER_OFFSET 0x01100000 //Keypad Row 0 Wakeup Key Enable Register
#define KR1_WKER_OFFSET 0x01200000 //Keypad Row 1 Wakeup Key Enable Register
#define KIDS_OFFSET 0x01300000 //Keypad ID Status
#define ISCR1_OFFSET 0x01400000 //Interrupt Status Control Register 1
#define ISCR2_OFFSET 0x01500000 //Interrupt Status Control Register 2
#define ISCR3_OFFSET 0x01600000 //Interrupt Status Control Register 3
#define IPCR1_OFFSET 0x01700000 //Interrupt Pending Control Register 1
#define IPCR2_OFFSET 0x01800000 //Interrupt Pending Control Register 2
#define IPCR3_OFFSET 0x01900000 //Interrupt Pending Control Register 3
#define IECR1_OFFSET 0x01A00000 //Interrupt Enable Control Register 1
#define IECR2_OFFSET 0x01B00000 //Interrupt Enable Control Register 2
#define IECR3_OFFSET 0x01C00000 //Interrupt Enable Control Register 3
#define IWECR1_OFFSET 0x01D00000 //Interrupt Wakeup Enable Control Register 1
#define IWECR2_OFFSET 0x01E00000 //Interrupt Wakeup Enable Control Register 2
#define IWECR3_OFFSET 0x01F00000 //Interrupt Wakeup Enable Control Register 3
typedef struct
{
unsigned char CPLDVersion; // 0900_0000
unsigned char rsvd8[3]; //
unsigned long rsvd9[0x3FFFF]; //
unsigned char DCR1; // 0910_0000
unsigned char rsvd10[3]; //
unsigned long rsvd11[0x3FFFF]; //
unsigned char DCR2; // 0920_0000
unsigned char rsvd12[3]; //
unsigned long rsvd13[0x3FFFF]; //
unsigned char DCR3; // 0930_0B00
unsigned char rsvd14[3]; //
unsigned long rsvd15[0x3FFFF]; //
unsigned char DCR4; // 0940_0000
unsigned char rsvd16[3]; //
unsigned long rsvd17[0x3FFFF]; //
unsigned char DRCR1; // 0950_0000
unsigned char rsvd18[3]; //
unsigned long rsvd19[0x3FFFF]; //
unsigned char DRCR2; // 0960_0000
unsigned char rsvd20[3]; //
unsigned long rsvd21[0x3FFFF]; //
unsigned char KPSSKR; // 0970_0000
unsigned char rsvd22[3]; //
unsigned long rsvd23[0x3FFFF]; //
unsigned char MKC0; // 0980_0000
unsigned char rsvd24[3]; //
unsigned long rsvd25[0x3FFFF]; //
unsigned char MKC1; // 0990_0000
unsigned char rsvd26[3]; //
unsigned long rsvd27[0x3FFFF]; //
unsigned char MKC2; // 09A0_0000
unsigned char rsvd28[3]; //
unsigned long rsvd29[0x3FFFF]; //
unsigned char MKC3; // 09B0_0000
unsigned char rsvd30[3]; //
unsigned long rsvd31[0x3FFFF]; //
unsigned char MKC4; // 09C0_0000
unsigned char rsvd32[3]; //
unsigned long rsvd33[0x3FFFF]; //
unsigned char MKC5; // 09D0_0000
unsigned char rsvd34[3]; //
unsigned long rsvd35[0x3FFFF]; //
unsigned char MKC6; // 09E0_0000
unsigned char rsvd36[3]; //
unsigned long rsvd37[0x3FFFF]; //
unsigned char MKC7; // 09F0_0000
unsigned char rsvd38[3]; //
unsigned long rsvd39[0x3FFFF]; //
unsigned char KLCR; // 0A00_0000
unsigned char rsvd40[3]; //
unsigned long rsvd41[0x3FFFF]; //
unsigned char KR0_WKER; // 0A10_0000
unsigned char rsvd42[3]; //
unsigned long rsvd43[0x3FFFF]; //
unsigned char KR1_WKER; // 0A20_0000
unsigned char rsvd44[3]; //
unsigned long rsvd45[0x3FFFF]; //
unsigned char KIDS; // 0A30_0000
unsigned char rsvd46[3]; //
unsigned long rsvd47[0x3FFFF]; //
unsigned char ISCR1; // 0A40_0000
unsigned char rsvd48[3]; //
unsigned long rsvd49[0x3FFFF]; //
unsigned char ISCR2; // 0A50_0000
unsigned char rsvd50[3]; //
unsigned long rsvd51[0x3FFFF]; //
unsigned char ISCR3; // 0A60_0000
unsigned char rsvd52[3]; //
unsigned long rsvd53[0x3FFFF]; //
unsigned char IPCR1; // 0A70_0000
unsigned char rsvd54[3]; //
unsigned long rsvd55[0x3FFFF]; //
unsigned char IPCR2; // 0A80_0000
unsigned char rsvd56[3]; //
unsigned long rsvd57[0x3FFFF]; //
unsigned char IPCR3; // 0A90_0000
unsigned char rsvd58[3]; //
unsigned long rsvd59[0x3FFFF]; //
unsigned char IECR1; // 0AA0_0000
unsigned char rsvd60[3]; //
unsigned long rsvd61[0x3FFFF]; //
unsigned char IECR2; // 0AB0_0000
unsigned char rsvd62[3]; //
unsigned long rsvd63[0x3FFFF]; //
unsigned char IECR3; // 0AC0_0000
unsigned char rsvd64[3]; //
unsigned long rsvd65[0x3FFFF]; //
unsigned char IWECR1; // 0AD0_0000
unsigned char rsvd66[3]; //
unsigned long rsvd67[0x3FFFF]; //
unsigned char IWECR2; // 0AE0_0000
unsigned char rsvd68[3]; //
unsigned long rsvd69[0x3FFFF]; //
unsigned char IWECR3; // 0AF0_0000
unsigned char rsvd70[3]; //
unsigned long rsvd71[0x3FFFF]; //
} COREPLATFORM_CPLD_REGS, *PCOREPLATFORM_CPLD_REGS;
/*
typedef struct
{
UINT8 CPLDVersion;
} CPLD_VER_REGS, *P_CPLD_VER_REGS;
*/
// Device Control Register 1
/*
typedef struct
{
UINT8 DCR1;
} CPLD_DCR1_REGS, *P_CPLD_DCR1_REGS;
*/
#define CF_SLOT1_PWR_EN (1<<7) //1=enable, 0=disable
#define CF_SLOT0_PWR_EN (1<<6) //1=enable, 0=disable
#define SDMMC_SLOT2_PWR_EN (1<<5) //1=enable, 0=disable
#define SDMMC_SLOT1_PWR_EN (1<<4) //1=enable, 0=disable
#define SCAN_1D2D_PWR_EN (1<<3) //1=enable, 0=disable
#define GPS_PWR_EN (1<<2) //1=enable, 0=disable
#define RFID_PWR_EN (1<<1) //1=enable, 0=disable
#define SYNC_PWR_EN (1<<0) //1=enable, 0=disable
// Device Control Register 2
/*
typedef struct
{
UINT8 DCR2;
} CPLD_DCR2_REGS, *P_CPLD_DCR2_REGS;
*/
#define nCAMERA_OUTPUT_EN (1<<7) //0=enable, 1=disable
#define GSM_IGT_PWR_EN (1<<6) //1=enable, 0=disable
#define DEBUG_BOARD_PWR_EN (1<<5) //1=enable, 0=disable
#define BLUETOOTH_PWR_EN (1<<4) //1=enable, 0=disable
#define ECHO_PWR_EN (1<<3) //1=enable, 0=disable
#define AUDIO_PWR_EN (1<<2) //1=enable, 0=disable
#define nSPEAKER_ON_OFF (1<<1) //1=ON, 0=OFF
#define INTERNAL_LCD_EN (1<<0) //1=enable, 0=disable
// Device Control Register 3
/*
typedef struct
{
UINT8 DCR3;
} CPLD_DCR3_REGS, *P_CPLD_DCR3_REGS;
*/
#define USB_CLIENT_PWR_EN (1<<7) //1=enable, 0=disable
#define CAMERA_PWR_EN (1<<6) //1=enable, 0=disable
#define FLASH_LIGHT_PWR_EN (1<<5) //1=enable, 0=disable
#define CRADLE_5V_PWR_EN (1<<4) //1=enable, 0=disable
#define SIR_MODE_SELECT (1<<3) //1=FIR, 0=SIR
#define IRDA_POWER_DOWN (1<<2) //1=power down, 0=power enable
#define FINGER_PWR_EN (1<<1) //1=enable, 0=disable
#define USB_HUB_PWR_EN (1<<0) //1=enable, 0=disable
// Device Control Register 4
/*
typedef struct
{
UINT8 DCR4;
} CPLD_DCR4_REGS, *P_CPLD_DCR4_REGS;
*/
#define nSCAN_1D_PWR_EN (1<<7) //0=enable, 1=disable
#define nECHO_POWER_DOWN (1<<6) //0=power down, 1=power enable
#define CAMERA_POWER_DOWN (1<<5) //1=power down, 0=power enable
#define nWAKEUP_2D_SCAN (1<<4) //0=wakeup, 1=?
#define nTRIGGER_2D (1<<3) //0=Trigger, 1=?
#define nTRIGGER_1D (1<<2) //1=Trigger, 0=?
#define nGPS_WAKEUP (1<<1) //0=wakeup, 1=?
#define MSYSTEM_LOCK (1<<0) //0=lock, 1=unlock
//Device Reset Control Register 1
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