📄 k9f1g08.txt
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; generated by ARM C Compiler, ADS1.2 [Build 805]
; commandline [-errors .\err\k9F1G08.err -O2 -asm -cpu ARM920T -fs -DCOREVOLT_M100=130 -DOS_START_ADDR_OFFSET=0x02040000 "-IC:\Program Files\ARM\ADSv1_2\INCLUDE"]
CODE32
AREA ||.text||, CODE, READONLY
NF1G08_ReadPage PROC
;;;106 int NF1G08_ReadPage(U32 block,U32 page,U8 *buffer)
;;;107 {
000000 e0810300 ADD r0,r1,r0,LSL #6
;;;108
;;;109 int i;
;;;110 unsigned int blockPage;
;;;111 U32 Mecc, Secc;
;;;112 U8 *bufPt=buffer;
;;;113
;;;114 blockPage=(block<<6)+page;
;;;115 NF_RSTECC(); // Initialize ECC
000004 e3a0144e MOV r1,#0x4e000000
000008 e92d4010 STMFD sp!,{r4,lr} ;107
00000c e5913004 LDR r3,[r1,#4]
000010 e3833010 ORR r3,r3,#0x10
000014 e5813004 STR r3,[r1,#4]
;;;116 NF_MECC_UnLock();
000018 e5913004 LDR r3,[r1,#4]
00001c e3c33020 BIC r3,r3,#0x20
000020 e5813004 STR r3,[r1,#4]
;;;117
;;;118 NF_nFCE_L();
000024 e5913004 LDR r3,[r1,#4]
000028 e3c33002 BIC r3,r3,#2
00002c e5813004 STR r3,[r1,#4]
;;;119
;;;120 NF_CLEAR_RB();
000030 e5913020 LDR r3,[r1,#0x20]
000034 e3833004 ORR r3,r3,#4
000038 e5813020 STR r3,[r1,#0x20]
;;;121 NF_CMD(0x00); // Read command
00003c e3a0c000 MOV r12,#0
000040 e581c008 STR r12,[r1,#8]
;;;122 NF_ADDR(0); // Column (A[7:0]) = 0
000044 e581c00c STR r12,[r1,#0xc]
;;;123 NF_ADDR(0); // A[11:8]
000048 e581c00c STR r12,[r1,#0xc]
;;;124 NF_ADDR((blockPage)&0xff); // A[19:12]
00004c e20030ff AND r3,r0,#0xff
000050 e581300c STR r3,[r1,#0xc]
;;;125 NF_ADDR((blockPage>>8)&0xff); // A[27:20]
000054 e1a00800 MOV r0,r0,LSL #16
000058 e1a00c20 MOV r0,r0,LSR #24
00005c e581000c STR r0,[r1,#0xc]
;;;126
;;;127 NF_CMD(0x30); // 2'nd command
000060 e3a00030 MOV r0,#0x30
000064 e5810008 STR r0,[r1,#8]
;;;128 NF_DETECT_RB();
|L1.104|
000068 e5910020 LDR r0,[r1,#0x20]
00006c e3100004 TST r0,#4
000070 0afffffc BEQ |L1.104|
;;;129
;;;130 #if TRANS_MODE==C_LANG
;;;131 for(i=0;i<2048;i++) {
;;;132 *bufPt++=NF_RDDATA8(); // Read one page
;;;133 }
;;;134 #elif TRANS_MODE==DMA
;;;135 // Nand to memory dma setting
;;;136 rSRCPND=BIT_DMA0; // Init DMA src pending.
000074 e3a0eb80 MOV lr,#0x20000
000078 e3a0444a MOV r4,#0x4a000000
00007c e584e000 STR lr,[r4,#0]
;;;137 rDISRC0=NFDATA; // Nand flash data register
000080 e59f3170 LDR r3,|L1.504|
000084 e3a0044b MOV r0,#0x4b000000
000088 e5803000 STR r3,[r0,#0]
;;;138 rDISRCC0=(0<<1) | (1<<0); //arc=AHB,src_addr=fix
00008c e3a03001 MOV r3,#1
000090 e5803004 STR r3,[r0,#4]
;;;139 rDIDST0=(unsigned)bufPt;
000094 e5802008 STR r2,[r0,#8]
;;;140 rDIDSTC0=(0<<1) | (0<<0); //dst=AHB,dst_addr=inc;
000098 e580c00c STR r12,[r0,#0xc]
;;;141 rDCON0=(1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(0<<23)|(1<<22)|(2<<20)|(2048/4/4);
00009c e59f2158 LDR r2,|L1.508|
0000a0 e5802010 STR r2,[r0,#0x10]
;;;142 //Handshake,AHB,interrupt,(4-burst),whole,S/W,no_autoreload,word,count=128;
;;;143
;;;144 // DMA on and start.
;;;145 rDMASKTRIG0=(1<<1)|(1<<0);
0000a4 e3a02003 MOV r2,#3
0000a8 e5802020 STR r2,[r0,#0x20]
;;;146
;;;147 while(!(rSRCPND & BIT_DMA0)); // Wait until Dma transfer is done.
|L1.172|
0000ac e5940000 LDR r0,[r4,#0]
0000b0 e3100b80 TST r0,#0x20000
0000b4 0afffffc BEQ |L1.172|
;;;148
;;;149 rSRCPND=BIT_DMA0;
0000b8 e584e000 STR lr,[r4,#0]
;;;150
;;;151 #endif
;;;152
;;;153 NF_MECC_Lock();
0000bc e5910004 LDR r0,[r1,#4]
0000c0 e3800020 ORR r0,r0,#0x20
0000c4 e5810004 STR r0,[r1,#4]
;;;154
;;;155
;;;156 NF_RDDATA8();
0000c8 e5d10010 LDRB r0,[r1,#0x10]
;;;157 Mecc=NF_RDDATA();
0000cc e5910010 LDR r0,[r1,#0x10]
;;;158 rNFMECCD0=((Mecc&0xff00)<<8)|(Mecc&0xff);
0000d0 e20020ff AND r2,r0,#0xff
0000d4 e2003cff AND r3,r0,#0xff00
0000d8 e1822403 ORR r2,r2,r3,LSL #8
0000dc e5812014 STR r2,[r1,#0x14]
;;;159 rNFMECCD1=((Mecc&0xff000000)>>8)|((Mecc&0xff0000)>>16);
0000e0 e3c028ff BIC r2,r0,#0xff0000
0000e4 e3c22cff BIC r2,r2,#0xff00
0000e8 e1a02422 MOV r2,r2,LSR #8
0000ec e1a00400 MOV r0,r0,LSL #8
0000f0 e1820c20 ORR r0,r2,r0,LSR #24
0000f4 e5810018 STR r0,[r1,#0x18]
;;;160
;;;161
;;;162 NF_nFCE_H();
0000f8 e5910004 LDR r0,[r1,#4]
0000fc e3800002 ORR r0,r0,#2
000100 e5810004 STR r0,[r1,#4]
;;;163
;;;164 if ((rNFESTAT0&0x3) == 0x0){
000104 e5910024 LDR r0,[r1,#0x24]
000108 e3100003 TST r0,#3
;;;165 // Uart_Printf("ECC OK!\n");
;;;166 return OK;
;;;167 }
;;;168 else {
;;;169 //Uart_Printf("ECC FAIL!\n");
;;;170 return FAIL;
00010c 13a00000 MOVNE r0,#0
000110 03a00001 MOVEQ r0,#1 ;166
000114 e8bd8010 LDMFD sp!,{r4,pc} ;166
;;;171 }
;;;172
;;;173
;;;174 }
ENDP
Nand_Reset PROC
;;;176 void Nand_Reset(void)
;;;177 {
000118 e3a0044e MOV r0,#0x4e000000
;;;178 int i;
;;;179
;;;180 NF_nFCE_L();
00011c e5901004 LDR r1,[r0,#4]
000120 e3c11002 BIC r1,r1,#2
000124 e5801004 STR r1,[r0,#4]
;;;181
;;;182 NF_CLEAR_RB();
000128 e5901020 LDR r1,[r0,#0x20]
00012c e3811004 ORR r1,r1,#4
000130 e5801020 STR r1,[r0,#0x20]
;;;183 NF_CMD(0xFF); //reset command
000134 e3a010ff MOV r1,#0xff
000138 e5801008 STR r1,[r0,#8]
;;;184 NF_DETECT_RB();
|L1.316|
00013c e5901020 LDR r1,[r0,#0x20]
000140 e3110004 TST r1,#4
000144 0afffffc BEQ |L1.316|
;;;185
;;;186 NF_nFCE_H();
000148 e5901004 LDR r1,[r0,#4]
00014c e3811002 ORR r1,r1,#2
000150 e5801004 STR r1,[r0,#4]
;;;187
;;;188 }
000154 e1a0f00e MOV pc,lr
ENDP
NF1G08_Init PROC
;;;190 void NF1G08_Init(void)
;;;191 {
000158 e3a01e60 MOV r1,#0x600
;;;192 // for S3C2442
;;;193
;;;194 rNFCONF = (TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4)|(0<<0);
00015c e3a0044e MOV r0,#0x4e000000
000160 e5801000 STR r1,[r0,#0]
;;;195 // TACLS [14:12] CLE&ALE duration = HCLK*TACLS.
;;;196 // TWRPH0 [10:8] TWRPH0 duration = HCLK*(TWRPH0+1)
;;;197 // TWRPH1 [6:4] TWRPH1 duration = HCLK*(TWRPH1+1)
;;;198 // AdvFlash(R) [3] Advanced NAND, 0:256/512, 1:1024/2048
;;;199 // PageSize(R) [2] NAND memory page size
;;;200 // when [3]==0, 0:256, 1:512 bytes/page.
;;;201 // when [3]==1, 0:1024, 1:2048 bytes/page.
;;;202 // AddrCycle(R) [1] NAND flash addr size
;;;203 // when [3]==0, 0:3-addr, 1:4-addr.
;;;204 // when [3]==1, 0:4-addr, 1:5-addr.
;;;205 // BusWidth(R/W) [0] NAND bus width. 0:8-bit, 1:16-bit.
;;;206
;;;207 rNFCONT = (0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(0<<6)|(0<<5)|(1<<4)|(1<<1)|(1<<0);
000164 e3a01013 MOV r1,#0x13
000168 e5801004 STR r1,[r0,#4]
;;;208 // Lock-tight [13] 0:Disable lock, 1:Enable lock.
;;;209 // Soft Lock [12] 0:Disable lock, 1:Enable lock.
;;;210 // EnablillegalAcINT[10] Illegal access interupt control. 0:Disable, 1:Enable
;;;211 // EnbRnBINT [9] RnB interrupt. 0:Disable, 1:Enable
;;;212 // RnB_TrandMode[8] RnB transition detection config. 0:Low to High, 1:High to Low
;;;213 // SpareECCLock [6] 0:Unlock, 1:Lock
;;;214 // MainECCLock [5] 0:Unlock, 1:Lock
;;;215 // InitECC(W) [4] 1:Init ECC decoder/encoder.
;;;216 // Reg_nCE [1] 0:nFCE=0, 1:nFCE=1.
;;;217 // NANDC Enable [0] operating mode. 0:Disable, 1:Enable.
;;;218
;;;219 rNFSTAT = 0;
00016c e3a01000 MOV r1,#0
000170 e5801020 STR r1,[r0,#0x20]
;;;220
;;;221 Nand_Reset();
000174 eafffffe B Nand_Reset
;;;222 }
ENDP
NF1G08_IsBadBlock PROC
;;;225 int NF1G08_IsBadBlock(U32 block)
;;;226 {
000178 e1a01300 MOV r1,r0,LSL #6
;;;227 int i;
;;;228 unsigned int blockPage;
;;;229 U8 data;
;;;230
;;;231
;;;232 blockPage=(block<<6); // For 2'nd cycle I/O[7:5]
;;;233
;;;234 NF_nFCE_L();
00017c e3a0044e MOV r0,#0x4e000000
000180 e5902004 LDR r2,[r0,#4]
000184 e3c22002 BIC r2,r2,#2
000188 e5802004 STR r2,[r0,#4]
;;;235 NF_CLEAR_RB();
00018c e5902020 LDR r2,[r0,#0x20]
000190 e3822004 ORR r2,r2,#4
000194 e5802020 STR r2,[r0,#0x20]
;;;236
;;;237 NF_CMD(0x00); // Read command
000198 e3a02000 MOV r2,#0
00019c e5802008 STR r2,[r0,#8]
;;;238 NF_ADDR((2048+0)&0xff); // 2060 = 0x080c
0001a0 e580200c STR r2,[r0,#0xc]
;;;239 NF_ADDR(((2048+0)>>8)&0xff)
0001a4 e3a02008 MOV r2,#8
0001a8 e580200c STR r2,[r0,#0xc]
;;;240 NF_ADDR((blockPage)&0xff); // A[19:12]
0001ac e20120ff AND r2,r1,#0xff
0001b0 e580200c STR r2,[r0,#0xc]
;;;241 NF_ADDR((blockPage>>8)&0xff); // A[27:20]
0001b4 e1a01801 MOV r1,r1,LSL #16
0001b8 e1a01c21 MOV r1,r1,LSR #24
0001bc e580100c STR r1,[r0,#0xc]
;;;242
;;;243 NF_CMD(0x30); // 2'nd command
0001c0 e3a01030 MOV r1,#0x30
0001c4 e5801008 STR r1,[r0,#8]
;;;244 NF_DETECT_RB();
|L1.456|
0001c8 e5901020 LDR r1,[r0,#0x20]
0001cc e3110004 TST r1,#4
0001d0 0afffffc BEQ |L1.456|
;;;245
;;;246
;;;247 data=NF_RDDATA();
0001d4 e5901010 LDR r1,[r0,#0x10]
;;;248
;;;249 NF_nFCE_H();
0001d8 e5902004 LDR r2,[r0,#4]
0001dc e20110ff AND r1,r1,#0xff ;247
0001e0 e3822002 ORR r2,r2,#2
0001e4 e5802004 STR r2,[r0,#4]
;;;250
;;;251 if(data!=0xff)
0001e8 e35100ff CMP r1,#0xff
;;;252 {
;;;253 // Uart_Printf("[block %d has been marked as a bad block(%x)]\n",block,data);
;;;254 return FAIL;
;;;255 }
;;;256 else
;;;257 {
;;;258 return OK;
0001ec 03a00001 MOVEQ r0,#1
0001f0 13a00000 MOVNE r0,#0 ;254
0001f4 e1a0f00e MOV pc,lr ;254
|L1.504|
0001f8 4e000010 DCD 0x4e000010 ;254
|L1.508|
0001fc f8600080 DCD 0xf8600080 ;254
;;;259 }
;;;260
;;;261 }
ENDP
AREA ||.bss||, NOINIT, ALIGN=2
downloadProgramSize
||.bss$7||
% 4
AREA |area_number.1|, NOINIT, ALIGN=2
EXPORTAS |area_number.1|, ||.bss||
srcAddress
||.bss$12||
% 4
AREA |area_number.2|, NOINIT, ALIGN=2
EXPORTAS |area_number.2|, ||.bss||
targetBlock
||.bss$17||
% 4
AREA |area_number.3|, NOINIT, ALIGN=2
EXPORTAS |area_number.3|, ||.bss||
targetSize
||.bss$22||
% 4
AREA |area_number.4|, NOINIT, ALIGN=2
EXPORTAS |area_number.4|, ||.bss||
downloadAddress
||.bss$27||
% 4
END
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