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📄 init_pic24hj64gp210.s

📁 uCOS在PIC芯片中的移植：以PIC24HJ64GP210为例进行uCOS在Microchip芯片中的移植
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12 
	CLR SPI2STAT

; Feature=I2C1 - I2C configuration

; B7:0: receive register bits7:0
	MOV I2C1RCV, W0

; B9:0: address register bits9:0
	CLR I2C1ADD

; B8:0: baud rate generator bits 8:0
	CLR I2C1BRG

; B15=ACKSTAT B14=TRSTAT B10=BCL B9=GCSTAT B8=ADD10

; B7=IWCOL B6=I2COV B5=D_A B4=P B3=S B2=R_W B1=RBF B0=TBF
	CLR I2C1STAT

; B15=I2CEN B13=I2CSIDL B12=SCLREL B11=IPMIEN B10=A10M B9=DISSLW B8=SMEN

; B7=GCEN B6=STREN B5=ACKDT B4=ACKEN B3=RCEN B2=PEN B1=RSEN B0=SEN
	MOV #0x1000, W0
	MOV W0, I2C1CON

; Feature=I2C2 - I2C configuration

; B7:0: receive register bits7:0
	MOV I2C2RCV, W0

; B9:0: address register bits9:0
	CLR I2C2ADD

; B8:0: baud rate generator bits 8:0
	CLR I2C2BRG

; B15=ACKSTAT B14=TRSTAT B10=BCL B9=GCSTAT B8=ADD10

; B7=IWCOL B6=I2COV B5=D_A B4=P B3=S B2=R_W B1=RBF B0=TBF
	CLR I2C2STAT

; B15=I2CEN B13=I2CSIDL B12=SCLREL B11=IPMIEN B10=A10M B9=DISSLW B8=SMEN

; B7=GCEN B6=STREN B5=ACKDT B4=ACKEN B3=RCEN B2=PEN B1=RSEN B0=SEN
	MOV #0x1000, W0
	MOV W0, I2C2CON

; Feature=UART1 - UART 1 configuration
	CLR U1BRG                              ; UART1 baud rate generator
	MOV #0x8000, W0                        ; enabling UART flushes buffers
	MOV W0, U1MODE

; B15=UTXISEL1 B14=UTXINV B13=UTXISEL0 B11=UTXBRK B10=UTXEN B9=UTXBF B8=TRMT

; B7:6=URXISEL1:0 B5=ADDEN B4=RIDLE B3=PERR B2=FERR B1=OERR B0=URXDA
	MOV #0x0110, W0
	MOV W0, U1STA

; B15=UARTEN B13=USIDL B12=IREN B11=RTSMD B9:8=UEN1:0

; B7=WAKE B6=LPBACK B5=ABAUD B4=RXINV B3=BRGH B2:1=PDSEL1:0 B0=STSEL
	CLR U1MODE

; Feature=UART2 - UART 2 configuration
	CLR U2BRG                              ; UART2 baud rate generator
	MOV #0x8000, W0                        ; enabling UART flushes buffers
	MOV W0, U2MODE

; B15=UTXISEL1 B14=UTXINV B13=UTXISEL0 B11=UTXBRK B10=UTXEN B9=UTXBF B8=TRMT

; B7:6=URXISEL1:0 B5=ADDEN B4=RIDLE B3=PERR B2=FERR B1=OERR B0=URXDA
	MOV #0x0110, W0
	MOV W0, U2STA

; B15=UARTEN B13=USIDL B12=IREN B11=RTSMD B9:8=UEN1:0

; B7=WAKE B6=LPBACK B5=ABAUD B4=RXINV B3=BRGH B2:1=PDSEL1:0 B0=STSEL
	CLR U2MODE

; Feature=DMA1 - DMA  configuration

; B15:8=PWCOL7:0 B7:0=XWCOL7:0
	CLR DMACS0

; B11:8=LSTCH3:0 B7:0=PPST7:0
	CLR DMACS1

; B15:0=DSADR15:0
	CLR DSADR

; Initialize DMA CH0

; B15=CHEN B14=SIZE B13=DIR B12=HALF B11=NULLW

; B5:4=AMODE1:0 B1:0=MODE1:0
	CLR DMA0CON

; B15=FORCE B6:0=IRQSEL6:0
	CLR DMA0REQ

; B15:0: Primary DMA RAM Start Address bit15:0
	CLR DMA0STA

; B15:0: Secondary DMA RAM Start Address bit15:0
	CLR DMA0STB

; B15:0: Peripheral Address Register bits15:0
	CLR DMA0PAD

; B9:0: Transfer Count Register bits9:0
	CLR DMA0CNT

; Initialize DMA CH1

; B15=CHEN B14=SIZE B13=DIR B12=HALF B11=NULLW

; B5:4=AMODE1:0 B1:0=MODE1:0
	CLR DMA1CON

; B15=FORCE B6:0=IRQSEL6:0
	CLR DMA1REQ

; B15:0: Primary DMA RAM Start Address bit15:0
	CLR DMA1STA

; B15:0: Secondary DMA RAM Start Address bit15:0
	CLR DMA1STB

; B15:0: Peripheral Address Register bits15:0
	CLR DMA1PAD

; B9:0: Transfer Count Register bits9:0
	CLR DMA1CNT

; Initialize DMA CH2

; B15=CHEN B14=SIZE B13=DIR B12=HALF B11=NULLW

; B5:4=AMODE1:0 B1:0=MODE1:0
	CLR DMA2CON

; B15=FORCE B6:0=IRQSEL6:0
	CLR DMA2REQ

; B15:0: Primary DMA RAM Start Address bit15:0
	CLR DMA2STA

; B15:0: Secondary DMA RAM Start Address bit15:0
	CLR DMA2STB

; B15:0: Peripheral Address Register bits15:0
	CLR DMA2PAD

; B9:0: Transfer Count Register bits9:0
	CLR DMA2CNT

; Initialize DMA CH3

; B15=CHEN B14=SIZE B13=DIR B12=HALF B11=NULLW

; B5:4=AMODE1:0 B1:0=MODE1:0
	CLR DMA3CON

; B15=FORCE B6:0=IRQSEL6:0
	CLR DMA3REQ

; B15:0: Primary DMA RAM Start Address bit15:0
	CLR DMA3STA

; B15:0: Secondary DMA RAM Start Address bit15:0
	CLR DMA3STB

; B15:0: Peripheral Address Register bits15:0
	CLR DMA3PAD

; B9:0: Transfer Count Register bits9:0
	CLR DMA3CNT

; Initialize DMA CH4

; B15=CHEN B14=SIZE B13=DIR B12=HALF B11=NULLW

; B5:4=AMODE1:0 B1:0=MODE1:0
	CLR DMA4CON

; B15=FORCE B6:0=IRQSEL6:0
	CLR DMA4REQ

; B15:0: Primary DMA RAM Start Address bit15:0
	CLR DMA4STA

; B15:0: Secondary DMA RAM Start Address bit15:0
	CLR DMA4STB

; B15:0: Peripheral Address Register bits15:0
	CLR DMA4PAD

; B9:0: Transfer Count Register bits9:0
	CLR DMA4CNT

; Initialize DMA CH5

; B15=CHEN B14=SIZE B13=DIR B12=HALF B11=NULLW

; B5:4=AMODE1:0 B1:0=MODE1:0
	CLR DMA5CON

; B15=FORCE B6:0=IRQSEL6:0
	CLR DMA5REQ

; B15:0: Primary DMA RAM Start Address bit15:0
	CLR DMA5STA

; B15:0: Secondary DMA RAM Start Address bit15:0
	CLR DMA5STB

; B15:0: Peripheral Address Register bits15:0
	CLR DMA5PAD

; B9:0: Transfer Count Register bits9:0
	CLR DMA5CNT

; Initialize DMA CH6

; B15=CHEN B14=SIZE B13=DIR B12=HALF B11=NULLW

; B5:4=AMODE1:0 B1:0=MODE1:0
	CLR DMA6CON

; B15=FORCE B6:0=IRQSEL6:0
	CLR DMA6REQ

; B15:0: Primary DMA RAM Start Address bit15:0
	CLR DMA6STA

; B15:0: Secondary DMA RAM Start Address bit15:0
	CLR DMA6STB

; B15:0: Peripheral Address Register bits15:0
	CLR DMA6PAD

; B9:0: Transfer Count Register bits9:0
	CLR DMA6CNT

; Initialize DMA CH7

; B15=CHEN B14=SIZE B13=DIR B12=HALF B11=NULLW

; B5:4=AMODE1:0 B1:0=MODE1:0
	CLR DMA7CON

; B15=FORCE B6:0=IRQSEL6:0
	CLR DMA7REQ

; B15:0: Primary DMA RAM Start Address bit15:0
	CLR DMA7STA

; B15:0: Secondary DMA RAM Start Address bit15:0
	CLR DMA7STB

; B15:0: Peripheral Address Register bits15:0
	CLR DMA7PAD

; B9:0: Transfer Count Register bits9:0
	CLR DMA7CNT

; Feature=A2D1 - A2D 1 configuration
                    ; Turn off A2D before setting registers
	CLR AD1CON1

; B15:0=CSS31:16
	CLR AD1CSSH

; B15:0=CSS15:0
	CLR AD1CSSL

; B10:9=CH123NB1:0 B8=CH123SB B2:1=CH123NA1:0 B0=CH123SA
	CLR AD1CHS123

; B15=CH0NB B12:8=CH0SB4:0

; B7=CH0NA B4:0=CH0SA4:0
	CLR AD1CHS0

; B15:0=PCFG31:16
	CLR AD1PCFGH

; B15:0=PCFG15:0
	CLR AD1PCFGL

; B2:0=DMABL
	CLR AD1CON4

; B15=ADRC B12:8=SAMC4:0 B5:0=ADCS5:0
	CLR AD1CON3

; B15:13=VCFG2:0 B10=CSCNA B9:8=CHPS

; B7=BUFS B5:2=SMPI B1=BUFM B0=ALTS
	CLR AD1CON2

; B15=ADON B13=ADSIDL B12=ADDMBAM B10=AD12B B9:8=FORM

; B7:5=SSRC B3=SIMSAM B2=ASAM B1=SAMP B0=DONE
	CLR AD1CON1

; Feature=required - Interrupt flags cleared and interrupt configuration

; interrupt priorities IP

; B14:12=T1 B10:8=OC1 B6:4=IC1 B2:0=INTO
	MOV #0x4444, W0
	MOV W0, IPC0

; B14:12=T2 B10:8=OC2 B6:4=IC2 B2:0=DMA0
	MOV #0x4444, W0
	MOV W0, IPC1

; B14:12=U1RX B10:8=SPI1 B6:4=SPI1E B2:0=T3
	MOV #0x4444, W0
	MOV W0, IPC2

; B10:8=DMA1 B6:4=AD1 B2:0=U1TX
	MOV #0x4444, W0
	MOV W0, IPC3

; B14:12=CN B6:4=MI2C1 B2:0=SI2C1
	MOV #0x4444, W0
	MOV W0, IPC4

; B14:12=IC8 B10:8=IC7 B6:4=AD2 B2:0=INT1
	MOV #0x4444, W0
	MOV W0, IPC5

; B14:12=T4 B10:8=OC4 B6:4=OC3 B2:0=DMA2
	MOV #0x4444, W0
	MOV W0, IPC6

; B14:12=U2TX B10:8=U2RX B6:4=INT2 B2:0=T5
	MOV #0x4444, W0
	MOV W0, IPC7

; B14:12=C1 B10:8=C1RX B6:4=SPI2 B2:0=SPI2E
	MOV #0x4444, W0
	MOV W0, IPC8

; B14:12=IC5 B10:8=IC4 B6:4=IC3 B2:0=DMA3
	MOV #0x4444, W0
	MOV W0, IPC9

; B14:12=OC7 B10:8=OC6 B6:4=OC5 B2:0=IC6
	MOV #0x4444, W0
	MOV W0, IPC10

; B14:12=T6 B10:8=DMA4 B2:0=OC8
	MOV #0x4444, W0
	MOV W0, IPC11

; B14:12=T8 B10:8=MI2C2 B6:4=SI2C2 B2:0=T7
	MOV #0x4444, W0
	MOV W0, IPC12

; B14:12=C2RX B10:8=INT4 B6:4=INT3 B2:0=T9
	MOV #0x4444, W0
	MOV W0, IPC13

; B2:0=C2
	MOV #0x4444, W0
	MOV W0, IPC14

; B6:4=DMA5
	MOV #0x4444, W0
	MOV W0, IPC15

; B10:8=U2E B6:4=U1E
	MOV #0x4444, W0
	MOV W0, IPC16

; B14:12=C2TX B10:8=C1TX B6:4=DMA7 B2:0=DMA6
	MOV #0x4444, W0
	MOV W0, IPC17

; external interrupt enables

; B15=NSTDIS B14=OVAERR B13=OVBERR B12=COVAERR B11=COVBERR B10=OVATE B9=OVBTE B8=COVTE

; B7=SFTACERR B6=DIV0ERR B5=DMACERR B4=MATHERR B3=ADDRERR B2=STKERR B1=OSCFAIL
	MOV #0x8000, W0
	MOV W0, INTCON1

; B15=ALTIVT B14=DISI B4:0=INTnEP4:0
	CLR INTCON2

; Feature=Timer1 - Start timers

; Timers1: B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B2=TSYNC B1=TCS
	CLR T1CON

; Feature=Timer3 - Start timers

; Timers3,5:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B1=TCS
	CLR T3CON

; Feature=Timer2 - Start timers

; Timers2,4:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B3=T32 B1=TCS
	CLR T2CON

; Feature=Timer5 - Start timers

; Timers3,5:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B1=TCS
	CLR T5CON

; Feature=Timer4 - Start timers

; Timers2,4:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B3=T32 B1=TCS
	CLR T4CON

; Feature=Timer7 - Start timers

; Timers7,9:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B1=TCS
	CLR T7CON

; Feature=Timer6 - Start timers

; Timers6,8:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B3=T32 B1=TCS
	CLR T6CON

; Feature=Timer9 - Start timers

; Timers7,9:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B1=TCS
	CLR T9CON

; Feature=Timer8 - Start timers

; Timers6,8:   B15=TON B13=TSIDL B5=TGATE B5:4=TCKPS1:0 B3=T32 B1=TCS
	CLR T8CON

; Feature=CPU - CPU register configuration
	CLR SR
	MOV #0x0080, W0
	MOV W0, SR
	CLR W0
	CLR W1
	CLR W2

; Feature=Interrupts - enable interrupts

; feature interrupt enables IE

; B14=DMA1 B13=AD1 B12=U1TX B11=U1RX B10=SPI1 B9=SPI1E B8=T3

; B7=T2 B6=OC2 B5=IC2 B4=DMA0 B3=T1 B2=OC1 B1=IC1 B0=INT0
	MOV #0x0001, W0
	MOV W0, IEC0

; B15=U2TX B14=U2RX B13=INT2 B12=T5 B11=T4 B10=OC4 B9=OC3 B8=DMA2

; B7=IC8 B6=IC7 B5=AD2 B4=INT1 B3=CN B1=MI2C1 B0=SI2C1
	MOV #0x2010, W0
	MOV W0, IEC1

; B15=T6 B14=DMA4 B12:9=OC8:5 B8:5=IC6:3 B4=DMA3 B3=C1 B2=C1RX B1=SPI2 B0=SPI2E
	CLR IEC2

; B13=DMA5 B8=C2

; B7=C2RX B6=INT4 B5=INT3 B4=T9 B3=T8 B2=MI2C2 B1=SI2C1 B0=T7
	MOV #0x0020, W0
	MOV W0, IEC3

; B7=C2TX B6=C1TX B5=DMA7 B4=DMA6 B2=U2E B1=U1E
	CLR IEC4

	return
12

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