📄 init_pic24hj64gp210.s
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; Initialization Code for PIC24HJ64GP210, Family: GP control, Package: 100-Pin TQFP 100pins
.include "p24HJ64GP210.inc"
; Filter Controls used to Generate Code:
; POR Match Filter OFF
; Provisioned Feature Filter OFF
; Masks are Ignored and uses UnMasked Register Writes
.GLOBAL _VisualInitialization
; Feature=fuses - fuses (DCR) configuration
; B1=GCP B0=GWRP
config __FGS, 0x803F
; B2:0=FNOSC2:0
config __FOSCSEL, 0x803B
; B7:6=FCKSM1:0 B2=OSCIOFNC B1:0=POSCMD1:0
config __FOSC, 0x80FC
; B7=FWDTEN B6=WINDIS B4=WDTPRE B3:0=WDTPOST3:0
config __FWDT, 0x803F
; B3=PWRTEN B2:0=FPWRT2:0
config __FPOR, 0x803F
.text
_VisualInitialization:
; Feature=Interrupts - Disable Interrupts during configuration
; clear int flags:
; B14=DMA1 B13=AD1 B12=U1TX B11=U1RX B10=SPI1 B9=SPI1E B8=T3
; B7=T2 B6=OC2 B5=IC2 B4=DMA0 B3=T1 B2=OC1 B1=IC1 B0=INT0
CLR IFS0
; B15=U2TX B14=U2RX B13=INT2 B12=T5 B11=T4 B10=OC4 B9=OC3 B8=DMA2
; B7=IC8 B6=IC7 B5=AD2 B4=INT1 B3=CN B1=MI2C1 B0=SI2C1
CLR IFS1
; B15=T6 B14=DMA4 B12:9=OC8:5 B8=IC6
; B7=IC5 B6=IC4 B5=IC3 B4=DMA3 B3=C1 B2=C1RX B1=SPI2 B0=SPI2E
CLR IFS2
; B13=DMA5 B8=C2
; B7=C2RX B6=INT4 B5=INT3 B4=T9 B3=T8 B2=MI2C2 B1=SI2C1 B0=T7
CLR IFS3
; B7=C2TX B6=C1TX B5=DMA7 B4=DMA6 B2=U2E B1=U1E B0=FLTB
CLR IFS4
CLR IEC0
CLR IEC1
CLR IEC2
CLR IEC3
CLR IEC4
; Feature=Reset - Reset configuration
; B15=TRAPR B14=IOPUWR B13=BGST B8=VREGS
; B7=EXTR B6=SWR B5=SWDTEN B4=WDTO B3=SLEEP B2=IDLE B1=BOR B0=POR
MOV #0x0503, W0
MOV W0, RCON
; Feature=NVM - NVM configuration - not implemented
; Feature=Oscillator - Oscillator configuration
; method to override OSCCON write protect
; B13:12=COSC1:0 B9:8=NOSC1:0
CLR.B W0
MOV.B #0x78, W1
MOV.B #0x9A, W2
MOV.W #OSCCON, W3
MOV.B W1, [W3+1]
MOV.B W2, [W3+1]
MOV.B W0, [W3+1]
; B7=CLKLOCK B5=LOCK B3=CF B1=LPOSCEN B0=OSWEN
CLR.B W0
MOV.B #0x46, W1
MOV.B #0x57, W2
MOV.B W1, [W3+0]
MOV.B W2, [W3+0]
MOV.B W0, [W3+0]
; B15=ROI B14:12=DOZE2:0 B11=DOZEN B10:8=FRCDIV2:0
; B7:6=PLLPOST1:0 B4:0=PLLPRE4:0
MOV #0x5800, W0
MOV W0, CLKDIV
; B8:0=PLLDIV8:0
CLR PLLFBD
; B5:0=TUN5:0
CLR OSCTUN
; Feature=A2D - A2D configuration
; Feature=IOPortA - IO Ports configuration
; B15:0=A15:0
CLR PORTA ; enable
MOV #0xFFFF, W0 ; direction in=1
MOV W0, TRISA
CLR ODCA ; direction in=1
; Feature=IOPortB - IO Ports configuration
; B15:0=B15:0
CLR PORTB ; enable
MOV #0xFFFF, W0 ; direction in=1
MOV W0, TRISB
; Feature=IOPortC - IO Ports configuration
; B15:0=C15:0
CLR PORTC ; enable
MOV #0xFFFF, W0 ; direction in=1
MOV W0, TRISC
; Feature=IOPortD - IO Ports configuration
; B15:0=D15:0
CLR PORTD ; enable
MOV #0xFFFF, W0 ; direction in=1
MOV W0, TRISD
CLR ODCD ; direction in=1
; Feature=IOPortE - IO Ports configuration
; B15:0=D15:0
CLR PORTE ; enable
MOV #0xFFFF, W0 ; direction in=1
MOV W0, TRISE
; Feature=IOPortF - IO Ports configuration
; B15:0=F15:0
CLR PORTF ; enable
MOV #0xFFFF, W0 ; direction in=1
MOV W0, TRISF
CLR ODCF ; direction in=1
; Feature=IOPortG - IO Ports configuration
; B15:0=G15:0
CLR PORTG ; enable
MOV #0xFFFF, W0 ; direction in=1
MOV W0, TRISG
CLR ODCG ; direction in=1
; Feature=CN1 - Input Change Notification configuration
; B15:0=CN15:0
CLR CNEN1 ; enable change notification
CLR CNPU1 ; enable pullup change notification
; B15:0=CN23:16 B7:0=CN7:0
CLR CNEN2 ; enable change notification
CLR CNPU2 ; enable pullup change notification
; Feature=CPU - CPU register configuration
CLR SR
MOV #0x0080, W0
MOV W0, SR
CLR W0
CLR W1
CLR W2
; Feature=Timer1 - Timers configuration
CLR T1CON ; stop timer
; Feature=Timer2 - Timers configuration
CLR T2CON ; stop timer
; Feature=Timer3 - Timers configuration
CLR T3CON ; stop timer
; Feature=Timer4 - Timers configuration
CLR T4CON ; stop timer
; Feature=Timer5 - Timers configuration
CLR T5CON ; stop timer
; Feature=Timer6 - Timers configuration
CLR T6CON ; stop timer
; Feature=Timer7 - Timers configuration
CLR T7CON ; stop timer
; Feature=Timer8 - Timers configuration
CLR T8CON ; stop timer
; Feature=Timer9 - Timers configuration
CLR T9CON ; stop timer
; Feature=Timer1 - Timers configuration
CLR TMR1 ; timer register
MOV #0xFFFF, W0 ; period register
MOV W0, PR1
; Feature=Timer3 - Timers configuration
CLR TMR3 ; timer register
CLR TMR3HLD ; timer holding register for 32bit
MOV #0xFFFF, W0 ; period register
MOV W0, PR3
; Feature=Timer2 - Timers configuration
CLR TMR2 ; timer register
MOV #0xFFFF, W0 ; period register
MOV W0, PR2
; Feature=Timer5 - Timers configuration
CLR TMR4 ; timer register
MOV #0xFFFF, W0 ; period register
MOV W0, PR4
; Feature=Timer4 - Timers configuration
CLR TMR5 ; timer register
CLR TMR5HLD ; timer holding register for 32bit
MOV #0xFFFF, W0 ; period register
MOV W0, PR5
; Feature=Timer6 - Timers configuration
CLR TMR6 ; timer register
MOV #0xFFFF, W0 ; period register
MOV W0, PR6
; Feature=Timer7 - Timers configuration
CLR TMR7 ; timer register
CLR TMR7HLD ; timer holding register for 32bit
MOV #0xFFFF, W0 ; period register
MOV W0, PR7
; Feature=Timer8 - Timers configuration
CLR TMR8 ; timer register
MOV #0xFFFF, W0 ; period register
MOV W0, PR8
; Feature=Timer9 - Timers configuration
CLR TMR9 ; timer register
CLR TMR9HLD ; timer holding register for 32bit
MOV #0xFFFF, W0 ; period register
MOV W0, PR9
; Feature=IC1 - Input Capture configuration
; B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0
CLR IC1CON
; Feature=IC2 - Input Capture configuration
; B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0
CLR IC2CON
; Feature=IC3 - Input Capture configuration
; B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0
CLR IC3CON
; Feature=IC4 - Input Capture configuration
; B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0
CLR IC4CON
; Feature=IC5 - Input Capture configuration
; B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0
CLR IC5CON
; Feature=IC6 - Input Capture configuration
; B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0
CLR IC6CON
; Feature=IC7 - Input Capture configuration
; B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0
CLR IC7CON
; Feature=IC8 - Input Capture configuration
; B13=ICSDL B7=ICTMR B6:5=ICI1:0 B4=ICOV B3=ICBNE B2:0=ICM2:0
CLR IC8CON
; Feature=OC1 - Turn off OC1 thru OC8
; associated timers need to be turned off first
CLR OC1CON
; Feature=OC2 - Turn off OC1 thru OC8
; associated timers need to be turned off first
CLR OC2CON
; Feature=OC3 - Turn off OC1 thru OC8
; associated timers need to be turned off first
CLR OC3CON
; Feature=OC4 - Turn off OC1 thru OC8
; associated timers need to be turned off first
CLR OC4CON
; Feature=OC5 - Turn off OC1 thru OC8
; associated timers need to be turned off first
CLR OC5CON
; Feature=OC6 - Turn off OC1 thru OC8
; associated timers need to be turned off first
CLR OC6CON
; Feature=OC7 - Turn off OC1 thru OC8
; associated timers need to be turned off first
CLR OC7CON
; Feature=OC8 - Turn off OC1 thru OC8
; associated timers need to be turned off first
CLR OC8CON
; Feature=OC1 - Output Compare configuration
; OCnRS: output compare n secondary register
; OCnR: output compare 1 main register
; OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0
CLR OC1RS
CLR OC1R
CLR OC1CON
; Feature=OC2 - Output Compare configuration
; OCnRS: output compare n secondary register
; OCnR: output compare 1 main register
; OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0
CLR OC2RS
CLR OC2R
CLR OC2CON
; Feature=OC3 - Output Compare configuration
; OCnRS: output compare n secondary register
; OCnR: output compare 1 main register
; OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0
CLR OC3RS
CLR OC3R
CLR OC3CON
; Feature=OC4 - Output Compare configuration
; OCnRS: output compare n secondary register
; OCnR: output compare 1 main register
; OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0
CLR OC4RS
CLR OC4R
CLR OC4CON
; Feature=OC5 - Output Compare configuration
; OCnRS: output compare n secondary register
; OCnR: output compare 1 main register
; OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0
CLR OC5RS
CLR OC5R
CLR OC5CON
; Feature=OC6 - Output Compare configuration
; OCnRS: output compare n secondary register
; OCnR: output compare 1 main register
; OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0
CLR OC6RS
CLR OC6R
CLR OC6CON
; Feature=OC7 - Output Compare configuration
; OCnRS: output compare n secondary register
; OCnR: output compare 1 main register
; OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0
CLR OC7RS
CLR OC7R
CLR OC7CON
; Feature=OC8 - Output Compare configuration
; OCnRS: output compare n secondary register
; OCnR: output compare 1 main register
; OCnCON: B13=OCSIDL B4=OCFLT B3=OCTSEL B2:0=OCM2:0
CLR OC8RS
CLR OC8R
CLR OC8CON
; Feature=SPI1 - SPI configuration
; SPInBUF: SPI n buffer
; SPInSTAT: B15=SPIEN B13=SPISIDL B6=SPIROV B1=SPITBF B0=SPIRBF
; SPInCON1(H): B12=DISSCK B11=DISSDO B10=MODE16 B9=SMP B8=CKE
; SPInCON1(L): B7=SSEN B6=CKP B5=MSTEN B4:2=SPRE2:0 B1:0=PPRE1:0
; SPInCON2(H): B15=FRMEN B14=SPIFSD B13=FRMPOL
; SPInCON2(L): B1=FRMDLY
MOV SPI1BUF, W0
CLR SPI1CON1
CLR SPI1CON2
CLR SPI1STAT
; Feature=SPI2 - SPI configuration
; SPInBUF: SPI n buffer
; SPInSTAT: B15=SPIEN B13=SPISIDL B6=SPIROV B1=SPITBF B0=SPIRBF
; SPInCON1(H): B12=DISSCK B11=DISSDO B10=MODE16 B9=SMP B8=CKE
; SPInCON1(L): B7=SSEN B6=CKP B5=MSTEN B4:2=SPRE2:0 B1:0=PPRE1:0
; SPInCON2(H): B15=FRMEN B14=SPIFSD B13=FRMPOL
; SPInCON2(L): B1=FRMDLY
MOV SPI2BUF, W0
CLR SPI2CON1
CLR SPI2CON2
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