uart1.scl

uCOS在PIC芯片中的移植：以PIC24HJ64GP210为例进行uCOS在Microchip芯片中的移植

// 
// D:\Massage\Micrium\Software\EvalBoards\Microchip\PIC24HJ\MPLAB\OS-View\Generated Files\UART1.scl
// Generated by Stimulus ver. 3.60.00.00
// 6/18/2008 14:43:04
// 


configuration for "pic24hj64gp210" is
end configuration;


testbench for "pic24hj64gp210" is
begin
    process is
    begin
        wait;
    end process;

    // Register Injection (message-based)
    process is
        file     data_file_U1RXREG  : text;
        variable pkt_line_U1RXREG   : line;
        variable status_U1RXREG     : file_open_status;
        variable read_ok_U1RXREG    : boolean;
        variable waitime_U1RXREG  : time;
        variable rand_lower_U1RXREG,
                 rand_upper_U1RXREG : integer;
        variable rand_unit_U1RXREG  : string;
        variable randime_U1RXREG  : time;
        variable rand_seed1_U1RXREG : integer := 30301;
        variable rand_seed2_U1RXREG : integer := 22593;
        variable packet_U1RXREG     : string;
        variable dummy_U1RXREG      : integer;
        variable new_packet_U1RXREG : boolean := true;
    begin
        file_open(status_U1RXREG, data_file_U1RXREG, "D:\Massage\TestData\UART1In.TXT", read_mode);
        if status_U1RXREG == open_ok then
            while endfile(data_file_U1RXREG) == false loop
                readline(data_file_U1RXREG, pkt_line_U1RXREG);
                // skip empty line and comment line
                if match(pkt_line_U1RXREG, "") == true then // do nothing
                elsif match(pkt_line_U1RXREG, "//") == true then // do nothing
                else
                    if match(pkt_line_U1RXREG, "wait ") == true then
                        read(pkt_line_U1RXREG, dummy_U1RXREG); // to consume 'wait' command
                        read(pkt_line_U1RXREG, waitime_U1RXREG);
                        wait for waitime_U1RXREG;
                        new_packet_U1RXREG := true;
                    elsif match(pkt_line_U1RXREG, "rand ") == true then
                        read(pkt_line_U1RXREG, dummy_U1RXREG); // to consume 'rand' command
                        read(pkt_line_U1RXREG, rand_lower_U1RXREG);
                        read(pkt_line_U1RXREG, rand_upper_U1RXREG);
                        read(pkt_line_U1RXREG, rand_unit_U1RXREG);
                        random_time(rand_lower_U1RXREG, rand_upper_U1RXREG, rand_unit_U1RXREG,
                                    rand_seed1_U1RXREG, rand_seed2_U1RXREG, randime_U1RXREG);
                        wait for randime_U1RXREG;
                        new_packet_U1RXREG := true;
                    else
                        if new_packet_U1RXREG == true then
                            packetin(pkt_line_U1RXREG, U1RXREG, false); // new packet
                            wait until U1RXREG_packet_done;
                            new_packet_U1RXREG := false;
                        else
                            packetin(pkt_line_U1RXREG, U1RXREG, true); // append to previous
                            wait until U1RXREG_packet_done;
                        end if;
                    end if;
                end if;
            end loop;
        end if;
        file_close(data_file_U1RXREG);
    end process;

end testbench;