📄 testcfg_c.c
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/* Do *not* directly modify this file. It was *//* generated by the Configuration Tool; any *//* changes risk being overwritten. *//* INPUT test.cdb *//* Include Header File */#include "testcfg.h"#ifdef __cplusplus#pragma CODE_SECTION(".text:CSL_cfgInit")#else#pragma CODE_SECTION(CSL_cfgInit,".text:CSL_cfgInit")#endif#ifdef __cplusplus#pragma FUNC_EXT_CALLED()#else#pragma FUNC_EXT_CALLED(CSL_cfgInit)#endif/* Config Structures */EMIF_Config emifCfg0 = { 0x0220, /* Global Control Register */ 0x0000, /* Global Reset Register */ 0x3fff, /* CE0 Space Control Register 1 */ 0x5fff, /* CE0 Space Control Register 2 */ 0x5fff, /* CE0 Space Control Register 3 */ 0x3fff, /* CE1 Space Control Register 1 */ 0x5fff, /* CE1 Space Control Register 2 */ 0x5fff, /* CE1 Space Control Register 3 */ 0x1fff, /* CE2 Space Control Register 1 */ 0x5fff, /* CE2 Space Control Register 2 */ 0x5fff, /* CE2 Space Control Register 3 */ 0x1fff, /* CE3 Space Control Register 1 */ 0x5fff, /* CE3 Space Control Register 2 */ 0x5fff, /* CE3 Space Control Register 3 */ 0x3922, /* SDRAM Control Register 1 */ 0x0400, /* SDRAM Period Register */ 0x0000, /* SDRAM Initialization Register */ 0x0252 /* SDRAM Control Register 2 */};PLL_Config pllCfg0 = { 0x0000, /* PLL Response After Idle (IAI) */ 0x0000, /* Response to Loss of PLL Core Lock (IOB) */ 0x0008, /* PLL Multiply Value (PLL_MULT) */ 0x0001 /* PLL Divide Value (PLL_DIV) */};/* Handles *//* * ======== CSL_cfgInit() ======== */void CSL_cfgInit(){ /* You must use DMA_start() in your main code to start the DMA. */ /* You must use MCBSP_start() in your main code to start the MCBSP. */ }
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