read_flashcfg_c.c

dsp 5509a 存储器测试, SDRAM 测试程序,12Mx16=192/2=96Msdram 时钟

/*   Do *not* directly modify this file.  It was    */
/*   generated by the Configuration Tool; any  */
/*   changes risk being overwritten.                */

/* INPUT read_flash.cdb */

/*  Include Header File  */
#include "read_flashcfg.h"


#ifdef __cplusplus
#pragma CODE_SECTION(".text:CSL_cfgInit")
#else
#pragma CODE_SECTION(CSL_cfgInit,".text:CSL_cfgInit")
#endif


#ifdef __cplusplus
#pragma FUNC_EXT_CALLED()
#else
#pragma FUNC_EXT_CALLED(CSL_cfgInit)
#endif


/*  Config Structures */
DMA_Config dmaCfg0 = {
    0x0000,        /*  Source Destination Register (CSDP)  */
    0x0000,        /*  Control Register (CCR)  */
    0x0000,        /*  Interrupt Control Register (CICR)  */
    NULL,        /*  Lower Source Address (CSSA_L) - Symbolic(Byte Address)  */
    NULL,        /*  Upper Source Address (CSSA_U) - Symbolic(Byte Address)  */
    NULL,        /*  Lower Destination Address (CDSA_L) - Symbolic(Byte Address)  */
    NULL,        /*  Upper Destination Address (CDSA_U) - Symbolic(Byte Address)  */
    0x0001,        /*  Element Number (CEN)  */
    0x0001,        /*  Frame Number (CFN)  */
    0x0000,        /*  Frame Index (CFI)  */
    0x0000         /*  Element Index (CEI)  */
};

EMIF_Config emifCfg0 = {
    0x0220,        /*  Global Control Register   */
    0x0000,        /*  Global Reset Register   */
    0x3fff,        /*  CE0 Space Control Register 1   */
    0x5fff,        /*  CE0 Space Control Register 2   */
    0x5fff,        /*  CE0 Space Control Register 3   */
    0x3fff,        /*  CE1 Space Control Register 1   */
    0x5fff,        /*  CE1 Space Control Register 2   */
    0x0000,        /*  CE1 Space Control Register 3   */
    0x1fff,        /*  CE2 Space Control Register 1   */
    0x5fff,        /*  CE2 Space Control Register 2   */
    0x0000,        /*  CE2 Space Control Register 3   */
    0x1fff,        /*  CE3 Space Control Register 1   */
    0x5fff,        /*  CE3 Space Control Register 2   */
    0x0000,        /*  CE3 Space Control Register 3   */
    0x3922,        /*  SDRAM Control Register 1   */
    0x0400,        /*  SDRAM Period Register   */
    0x0000,        /*  SDRAM Initialization Register   */
    0x0252         /*  SDRAM Control Register 2   */
};

MCBSP_Config mcbspCfg0 = {
    0x1800,        /*  Serial Port Control Register 1   */
    0x0000,        /*  Serial Port Control Register 2   */
    0x0700,        /*  Receive Control Register 1   */
    0x0005,        /*  Receive Control Register 2   */
    0x0700,        /*  Transmit Control Register 1   */
    0x0005,        /*  Transmit Control Register 2   */
    0x000b,        /*  Sample Rate Generator Register 1   */
    0x2000,        /*  Sample Rate Generator Register 2   */
    0x0000,        /*  Multichannel Control Register 1   */
    0x0000,        /*  Multichannel Control Register 2   */
    0x0e09,        /*  Pin Control Register   */
    0x0000,        /*  Receive Channel Enable Register Partition A   */
    0x0000,        /*  Receive Channel Enable Register Partition B   */
    0x0000,        /*  Receive Channel Enable Register Partition C   */
    0x0000,        /*  Receive Channel Enable Register Partition D   */
    0x0000,        /*  Receive Channel Enable Register Partition E   */
    0x0000,        /*  Receive Channel Enable Register Partition F   */
    0x0000,        /*  Receive Channel Enable Register Partition G   */
    0x0000,        /*  Receive Channel Enable Register Partition H   */
    0x0000,        /*  Transmit Channel Enable Register Partition A   */
    0x0000,        /*  Transmit Channel Enable Register Partition B   */
    0x0000,        /*  Transmit Channel Enable Register Partition C   */
    0x0000,        /*  Transmit Channel Enable Register Partition D   */
    0x0000,        /*  Transmit Channel Enable Register Partition E   */
    0x0000,        /*  Transmit Channel Enable Register Partition F   */
    0x0000,        /*  Transmit Channel Enable Register Partition G   */
    0x0000         /*  Transmit Channel Enable Register Partition H   */
};

PLL_Config pllCfg0 = {
    0x0000,        /*  PLL Response After Idle (IAI)   */
    0x0000,        /*  Response to Loss of PLL Core Lock (IOB)   */
    0x0008,        /*  PLL Multiply Value (PLL_MULT)   */
    0x0000         /*  PLL Divide Value (PLL_DIV)   */
};

/*  Handles  */
MCBSP_Handle hMcbsp0;
MCBSP_Handle hMcbsp1;

/*
 *  ======== CSL_cfgInit() ========  
 */
void CSL_cfgInit()
{
        hMcbsp0 = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET);
    hMcbsp1 = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);
    EMIF_config(&emifCfg0);
    MCBSP_config(hMcbsp0, &mcbspCfg0);
    MCBSP_config(hMcbsp1, &mcbspCfg0);
    PLL_config(&pllCfg0);

    /* You must use DMA_start() in your main code to start the DMA. */

	
    
    /* You must use MCBSP_start() in your main code to start the MCBSP. */

    
    /* You must use RTC_start() in your main code to start the RTC. */

    
    /* You must use WDTIM_start() in your main code to start the WDTIM. */

}