fifo_link_v2_1_0.pao

DMA VHDL 设计IP核经常遇到大数据交换要用DMA

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## ** Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.            **
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## ** You may copy and modify these files for your own internal use solely  **
## ** with Xilinx programmable logic devices and Xilinx EDK system or       **
## ** create IP modules solely for Xilinx programmable logic devices and    **
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## Filename:          D:\mpdma\pcores\fifo_link_v1_00_a\data\fifo_link_v2_1_0.pao
## Description:       Peripheral Analysis Order
## Date:              Sun Oct 22 10:40:07 2006 (by Create and Import Peripheral Wizard)
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lib fifo_link_v1_00_a fifo_link vhdl