fifo_link_v2_1_0.mpd

DMA VHDL 设计IP核经常遇到大数据交换要用DMA

## Copyright (c) 2004 Xilinx, Inc. All Rights Reserved.
## You may copy and modify these files for your own internal use solely with
## Xilinx programmable logic devices and  Xilinx EDK system or create IP
## modules solely for Xilinx programmable logic devices and Xilinx EDK system.
## No rights are granted to distribute any files unless they are distributed in
## Xilinx programmable logic devices.
###################################################################
##
## Name     : fifo_link
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
###################################################################

BEGIN fifo_link

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION CORE_STATE = ACTIVE
OPTION IP_GROUP = MICROBLAZE:PPC:USER


## Bus Interfaces
BUS_INTERFACE BUS = SFSL, BUS_TYPE = SLAVE, BUS_STD = FSL
BUS_INTERFACE BUS = MFSL, BUS_TYPE = MASTER, BUS_STD = FSL

## Generics for VHDL or Parameters for Verilog

## Ports
PORT FSL_Clk = "", DIR = I, SIGIS = Clk, BUS = SFSL:MFSL
PORT FSL_Rst = OPB_Rst, DIR = I, BUS = SFSL:MFSL
PORT FSL_S_Clk = FSL_S_Clk, DIR = O, SIGIS = Clk, BUS = SFSL
PORT FSL_S_Read = FSL_S_Read, DIR = O, BUS = SFSL
PORT FSL_S_Data = FSL_S_Data, DIR = I, VEC = [0:31], BUS = SFSL
PORT FSL_S_Control = FSL_S_Control, DIR = I, BUS = SFSL
PORT FSL_S_Exists = FSL_S_Exists, DIR = I, BUS = SFSL
PORT FSL_M_Clk = FSL_M_Clk, DIR = O, SIGIS = Clk, BUS = MFSL
PORT FSL_M_Write = FSL_M_Write, DIR = O, BUS = MFSL
PORT FSL_M_Data = FSL_M_Data, DIR = O, VEC = [0:31], BUS = MFSL
PORT FSL_M_Control = FSL_M_Control, DIR = O, BUS = MFSL
PORT FSL_M_Full = FSL_M_Full, DIR = I, BUS = MFSL

END