pll.c

对于DSP自引导程序的一个实例

#ifndef _PLL_H_
#include "pll.h"
#endif


void PLL_INI();


/*----------------------------------------------------------------------------*/
/* PLL_INI() -- DSP PLL initiate:Set the frequence of SYSCLK1,SYSCLK2,SYSCLK3 
                                                                           
              EMIF   -- SYSCLK3
              EDMA   -- CPU CLOCK Frequence
              McBSPS -- SYSCLK2
              Timer  -- 1/4 of SYSCLK1    
     More detailed information in SPRU233a.pdf                                 */               
/*-----------------------------------------------------------------------------*/
void PLL_INI()
{	
/* Description:
    该程序主要完成DSP的各处时钟的设置
 
                Input clock CLKIN = 25MHz
                SYSCLK1(DSP core) = 200MHz
                SYSCLK2           = 100MHz
                SYSCLK3           = 100MHz
                CLKOUT3           = 25MHz
                
                PLLOUT            = 400MHz
                PLLREF            = 25MHz    
*/	                	
	int i;
	 *(unsigned volatile int *)PLLCSR  = 0x0;	// Must enter Bypass mode first
	for(i=0;i<32;i++);	                // Wait 4 cycles of the slowest of PLLOUT,
	
	*(unsigned volatile int *)PLLCSR  = 0x8;	//Reset and disable the PLL
	
	*(unsigned volatile int *)PLLDIV0 = 0x8000;	// PLLREF=25M/1=25M
	*(unsigned volatile int *)PLLM    = 0x10;	// PLLOUT=25M*16=400M     
	*(unsigned volatile int *)OSCDIV1 = 0x8000;  // CLKOUT3=25M/1=25M 
	for(i=0;i<64;i++);	      
	                                        //Wait 8 cycles of the slowest of the old and new SYSCLK1-3 clock rates
	*(unsigned volatile int *)PLLDIV3 = 0x8003;  // SYSCLK3=400M/4=100M  
	for(i=0;i<64;i++);	
	                                        //Wait 8 cycles of the slowest of the old and new SYSCLK1-3 clock rates
	*(unsigned volatile int *)PLLDIV2 = 0x8003;  // SYSCLK2=400M/4=100M,must be the half of f_CORE
	for(i=0;i<64;i++);	
	                                        //Wait 8 cycles of the slowest of the old and new SYSCLK1-3 clock rates

        *(unsigned volatile int *)PLLDIV1 = 0x8001;	 // SYSCLK1(DSP core)=400M/2=200M,must change after D1 when descend frequence
	for (i=0;i<4096;i++);			
	                                        //Wait for PLL to properly reset,512 CLKIN cycles ??
	*(unsigned volatile int *)PLLCSR  = 0x0;	// Bring PLL out of reset    
    	    									
	while ((*((unsigned volatile int *)PLLCSR) & 0x40)==0)	; 	//Wait for PLL to lock, STABLE=1

	*(unsigned volatile int *)PLLCSR = 0x1;	// Enable inter PLL	
}