emif.h

对于DSP自引导程序的一个实例

/**********************************************************/
//  emif.h - TMS320C6713 EMIF register address                              
//  v3.0     Jun 28th,2005 ,By Zhang G.Q , IPRAI
// The file Definites Register Address for TMS320CC6713   

/*********************************************************/
#ifndef _EMIF_H_
#define _EMIF_H_

//typedef unsigned int    DWORD;      /* 32-bit data type */
//typedef unsigned short  WORD;       /* 16-bit data type */
//typedef unsigned char   BYTE;       /* 8-bit data type */

/* Define EMIF Registers  */
#define EMIF_GBLCTL 0x1800000	/* Address of EMIF global control	*/
#define EMIF_CE0CTL	0x1800008	/* Address of EMIF CE0 control		*/
#define EMIF_CE1CTL	0x1800004	/* Address of EMIF CE1 control		*/
#define EMIF_CE2CTL	0x1800010	/* Address of EMIF CE2 control		*/
#define EMIF_CE3CTL	0x1800014	/* Address of EMIF CE3 control		*/
#define EMIF_SDCTL	0x1800018	/* Address of EMIF SDRAM control	*/
#define EMIF_SDTIM	0x180001c	/* Address of EMIF SDRAM refresh control*/
#define EMIF_SDEXT	0x1800020	/* Address of EMIF SDRAM extension	*/

/*Define the Device Register */
#define	DEVCFG		0x19c0200	/*Device Configuration register*/

/* Define L2 Cache Control Registers Addresses */
#define CCFG            0x1840000	/* Cache configuration register                    */
#define L2WBAR          0x1844000       /* L2 writeback base address register              */
#define L2WWC           0x1844004       /* L2 writeback word count register                */
#define L2WIBAR         0x1844010       /* L2 writeback-invalidate base register           */
#define L2WIWC          0x1844014       /* L2 writeback-invalidate base address register   */
#define L1PIBAR         0x1844020       /* L1P invalidate base address register            */
#define L1PIWC          0x1844024       /* L1P invalidate word count register              */
#define L1DWIBAR        0x1844030       /* L1D writeback-invalidate base address register  */
#define L1DWIWC         0x1844034       /* L1D writeback-invalidate word count register    */
#define L2WB            0x1845000       /* L2 writeback all register                       */
#define L2WBINV         0x1845004       /* L2 writeback-invalidate all registe             */
#define MAR0            0x1848200	/* Controls CE0 range 80000000h - 80FFFFFFh        */      
#define MAR1            0x1848204	/* Controls CE0 range 81000000h - 81FFFFFFh        */
#define MAR2            0x1848208	/* Controls CE0 range 82000000h - 82FFFFFFh        */
#define MAR3            0x184820C	/* Controls CE0 range 83000000h - 83FFFFFFh        */
#define MAR4            0x1848240	/* Controls CE1 range 90000000h - 90FFFFFFh        */
#define MAR5            0x1848244	/* Controls CE1 range 91000000h - 91FFFFFFh        */
#define MAR6            0x1848248	/* Controls CE1 range 92000000h - 92FFFFFFh        */
#define MAR7            0x184824C	/* Controls CE1 range 93000000h - 93FFFFFFh        */
#define MAR8            0x1848280	/* Controls CE2 range A0000000h - A0FFFFFFh        */
#define MAR9            0x1848284	/* Controls CE2 range A1000000h - A1FFFFFFh        */
#define MAR10           0x1848288	/* Controls CE2 range A2000000h - A2FFFFFFh        */
#define MAR11           0x184828C	/* Controls CE2 range A3000000h - A3FFFFFFh        */ 
#define MAR12           0x18482C0	/* Controls CE3 range B0000000h - B0FFFFFFh        */ 
#define MAR13           0x18482C4	/* Controls CE3 range B1000000h - B1FFFFFFh        */  
#define MAR14           0x18482C8	/* Controls CE3 range B2000000h - B2FFFFFFh        */ 
#define MAR15           0x18482CC	/* Controls CE3 range B3000000h - B3FFFFFFh        */  

/* EMIF Global Control Register (GBLCTL) */
#define CLK6EN                   3
#define CLK4EN                   4
#define EK1EN                    5
#define EK1HZ                    6
#define NOHOLD                   7
#define HOLDA                    8 
#define HOLD                     9
#define ARDY                    10
#define BUSREQ                  11
#define BRMODE                  13
#define EK2EN                   16
#define EK2HZ                   17
#define EK2RATE                 18

/*EMIF CE Space Control Register (CExCTL)*/
#define READHOLD                 0       /* Hold width   */
#define WRITEHOLDMSB             3
#define MTYPE                    4       /* Memory type of the corresponding CE spaces      */
#define READSTROBE               8       /* The width of read strobe (/ARE) in clock cycles */
#define TA                      14       /* Turn-around time                                */
#define READSETUP               16       /* Setup width  */
#define WRITEHOLD               20       /* Hold width   */
#define WRITESTROBE             22       /* The width of write strobe (/AWE) in clock cycles*/
#define WRITESETUP              28       /* Setup width  */

/*有关CE0,CE1,CE2的地址空间的定义*/
#define FPGA_START_ADR 	0x80000000		/* The Start Address of CE0 */
#define FLASH_START_ADR	0x90000000		/* The Start Address of CE1 */
#define	SDRAM_START_ADR	0xA0000000		/* The Start Address of CE2 */


//#define SDRAM_TEST_SIZE	0x00000400>>1	/* The size of SDRAM is 1M in 16bit,shift for 32bit */

#endif