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📄 boot_67_new.asm

📁 对于DSP自引导程序的一个实例
💻 ASM
字号:
        .title  "Flash bootup utility for 6713 "
;*************************************************************************************      
; EMIF registers and values   
;EMIFB_GCR      .equ    0x01A80000	;EMIF global control     
;EMIFB_CE0      .equ    0x01A80008	;EMIF CE0 control          
;EMIFB_CE1      .equ    0x01A80004	;address of EMIF CE1 control reg. 
;EMIFB_SDCTRL   .equ    0x01A80018	;EMIF SDRAM control     
;EMIFB_SDRP     .equ    0x01A8001c	;EMIF SDRM refresh period 
;EMIFB_SDEXT    .equ    0x01A80020    ;EMIF SDRAM extension

;EMIFB_GCR_V    .equ    0x33603360	;EMIF global control value      ;0x3360
;EMIFB_CE0_V    .equ    0x00900090	;EMIF CE0control value          ;0x90
;EMIFB_SDCTRL_V .equ    0x07227000	;EMIF SDRAM control value       ;0x07227000    
;EMIFB_SDRP_V   .equ    0x061a061a	;EMIF SDRM refresh period value ;0x061a
;EMIFB_SDEXT_V  .equ    0x00054529  ;EMIF SDRAM extension value   ;0x00054529

;EMIFB_CE1_8    .equ    0xffffff03	;
;EMIFB_CE1_32   .equ    0xffffff23	;
;************************************************************************************
; EMIF registers and values   
EMIF_GCR      .equ    0x01800000	;EMIF global control     
EMIF_CE0      .equ    0x01800008	;EMIF CE0 control          
EMIF_CE1      .equ    0x01800004	;address of EMIF CE1 control reg. 
EMIF_SDCTRL   .equ    0x01800018	;EMIF SDRAM control     
EMIF_SDRP     .equ    0x0180001c	;Address of EMIF SDRAM refresh control
EMIF_SDEXT    .equ    0x01800020    ;EMIF SDRAM extension

EMIF_GCR_V    .equ    0x37f837f8	;EMIF global control value      ;0x37f8
EMIF_CE0_V    .equ    0x14e1e012	;EMIF CE0control value          ;0x14e1e012
EMIF_SDCTRL_V .equ    0x57116000	;EMIF SDRAM control value       ;0x57116000    
EMIF_SDRP_V   .equ    0x061a061a	;EMIF SDRAM refresh period value;0x61a
EMIF_SDEXT_V  .equ    0x00054529    ;EMIF SDRAM extension value  	;0x54529

EMIF_CE1_8    .equ    0xffffff03	;
EMIF_CE1_32   .equ    0xffffff23	;







; QDMA registers and values
QDMA_OPT      .equ    0x02000000    ;QDMA options register
QDMA_SRC	  .equ	  0x02000004	;QDMA source address register
QDMA_CNT	  .equ	  0x02000008	;QDMA count register
QDMA_DST	  .equ	  0x0200000c	;QDMA destination address register
QDMA_IDX	  .equ	  0x02000010	;QDMA index register
QDMA_S_IDX    .equ    0x02000030    ;QDMA index pseudo-register

QDMA_OPT_VAL  .equ	  0x21200001	;QDMA options value

 
	.global _boot
	.global copy_table
;    .global _RelocateISTP
;    .global _MemCopy
;    .ref    _src
;    .ref    _dst
    .global  __vector  ; /* Memory location for default   */
	.ref _c_int00
	
_boot .sect ".boot_load" 
                                           
; **************       
; Configure EMIF                
; **************
                            
            mvkl  EMIF_GCR,A4		;EMIF_GCR address ->A4
      ||    mvkl  EMIF_GCR_V,B4      
            mvkh  EMIF_GCR,A4
      ||    mvkh  EMIF_GCR_V,B4                            
            stw   B4,*A4             

            mvkl  EMIF_CE0,A4       ;EMIF_CE0 address ->A4
      ||    mvkl  EMIF_CE0_V,B4     ;
            mvkh  EMIF_CE0,A4
      ||    mvkh  EMIF_CE0_V,B4     
            stw   B4,*A4

            mvkl  EMIF_CE1,A4       ;EMIF_CE1 address ->A4
      ||    mvkl  EMIF_CE1_8,B4    ;
            mvkh  EMIF_CE1,A4
      ||    mvkh  EMIF_CE1_8,B4
            stw   B4,*A4
    
            mvkl  EMIF_SDCTRL,A4    ;EMIF_SDCTRL address ->A4
      ||    mvkl  EMIF_SDCTRL_V,B4  ;
            mvkh  EMIF_SDCTRL,A4
      ||    mvkh  EMIF_SDCTRL_V,B4     
            stw   B4,*A4                

            mvkl  EMIF_SDRP,A4      ;EMIF_SDRP address ->A4
      ||    mvkl  EMIF_SDRP_V,B4			;
            mvkh  EMIF_SDRP,A4
      ||    mvkh  EMIF_SDRP_V,B4
            stw   B4,*A4   

            mvkl  EMIF_SDEXT,A4      ;EMIF_SDRP address ->A4
      ||    mvkl  EMIF_SDEXT_V,B4			;
            mvkh  EMIF_SDEXT,A4
      ||    mvkh  EMIF_SDEXT_V,B4
            stw   B4,*A4   

; *************            
; Copy Sections
; *************
S_R   .set	b4
D_R   .set	a4

	    	mvkl  copy_table, A3	; load table pointer
	    	mvkh  copy_table, A3

copy_section_top:	
	    	ldw   *A3++, B0			; load src copy lenth      B0 = cnt
	    	ldw   *A3++, A4			; load ram start address   A4 = (dst)
	    	ldw   *A3++, B4			; load flash start address B4 = (src)
	    	nop   2
	[!b0]   b	  copy_done			; have we copied all sections? 
	    	nop	  5
	    	
; copy this section with QDMA
			shr   B0,2,B1			; divide size by 4 (because we're in 32-bit mode)
	    	
copy_loop:
	        ldw        *S_R++,B5
  ||        mv         B1, A1       ;load dst copy lenth
  ||        sub        B1, 1, B1
  
	[B1]    ldw        *S_R++,B5
  ||[B1]    sub        B1, 1, B1
	[B1]    ldw        *S_R++,B5
  ||[B1]    sub        B1, 1, B1
	[B1]    ldw        *S_R++,B5
  ||[B1]    sub        B1, 1, B1
	[B1]    ldw        *S_R++,B5
  ||[B1]    sub        B1, 1, B1

            stw        B5,*D_R++
  ||        sub        A1, 1, A1
    [A1]    stw        B5,*D_R++
  ||[A1]    sub        A1, 1, A1
    [A1]    stw        B5,*D_R++
  ||[A1]    sub        A1, 1, A1
    [A1]    stw        B5,*D_R++
  ||[A1]    sub        A1, 1, A1
    [A1]    stw        B5,*D_R++
  ||[A1]    sub        A1, 1, A1
  
    [B1]    b          copy_loop                        
            nop        5

;*************************************************************  
;            ldw   *B4++,B5
;            nop   5
;            stw   B5,*A4++
;      ||    sub   .D2 B1, 1, B1
;     [B1]   b     copy_loop                        
;            nop   5
            
;*************************************************************            
; 			mvkl  QDMA_OPT,A5       ; set QDMA options
; 			mvkl  QDMA_OPT_VAL,B5
; 			mvkh  QDMA_OPT,A5
; 			mvkh  QDMA_OPT_VAL,B5
; 			stw   B5,*A5
; 			
; 			mvkl  QDMA_SRC,A5		; load source address
; 			mvkh  QDMA_SRC,A5      
; 			stw   B4,*A5
; 				        
;			shr   B0,2,B1			; divide size by 4 (because we're in 32-bit mode)
;			mvkl  QDMA_CNT,A5		; load word count
;			mvkh  QDMA_CNT,A5      
; 			stw   B1,*A5
; 			            
; 			mvkl  QDMA_DST,A5		; load destination address
; 			mvkh  QDMA_DST,A5      
; 			stw   A4,*A5
; 				  
;			mvkl  QDMA_S_IDX,A5		; set index. writing to this register will
; 			mvkh  QDMA_S_IDX,A5     ; also initiate the transfer.
; 			zero  B5
; 			stw   B5,*A5            ; go!
;*************************************************************  

; next section	           

			b	  copy_section_top
			nop   5

copy_done:  ; done with section copying.  
			; jump to _c_int00
			
;			mvkl  .s2 __vector,B0
;			mvkh  .s2 __vector,B0
;			mvc   B0,ISTP
        
			mvkl .S2 _c_int00, B0
            mvkh .S2 _c_int00, B0
            B    .S2 B0
            nop   5
               
               
; *************            
; Section Table
; *************
    ;; Table of sections to copy. Format is:
    ;; word 0:	byte count
    ;; word 1:	run address
    ;; word 2:	load address
    
copy_table:       
    ;; .vectors
;    .word 0x00000ac0
;    .word 0x00000400
;    .word 0x90000400
    ;; .text
    .word 0x00008dc0
    .word 0x00000400
    .word 0x90000400
    ;; .const
    .word 0x0000014c
    .word 0x000091c0
    .word 0x900091c0
    ;; .cinit
    .word 0x00000334
    .word 0x00009310
    .word 0x90009310
    ;; end of table
    .word 0
    .word 0
    .word 0              


	.text
;_RelocateISTP
;	mvkl  .s2 __vector,B0;
;	mvkh  .s2 __vector,B0
;	mvc   B0,ISTP
;	B b3
;	NOP 5


;*************************************************************
;My fast MemCopy Func
;*************************************************************
;copylen       .equ    10    ; MemCopy len (in INT32U)
;S_R   .set	b4
;D_R   .set	a4
;
;_MemCopy
;	    	mvkl  _src, S_R	; load copy src
;	    	mvkh  _src, S_R
;	    	mvkl  _dst, D_R	; load copy dst
;	    	mvkh  _dst, D_R
;	    	mvkl  copylen,  B1  ;load src copy lenth
;	    	mvkh  copylen,  B1
;Memcopy_loop:
;	        ldw        *S_R++,B5
;  ||        mv         B1, A1       ;load dst copy lenth
;  ||        sub        B1, 1, B1
;  
;	[B1]    ldw        *S_R++,B5
;  ||[B1]    sub        B1, 1, B1
;	[B1]    ldw        *S_R++,B5
;  ||[B1]    sub        B1, 1, B1
;	[B1]    ldw        *S_R++,B5
;  ||[B1]    sub        B1, 1, B1
;	[B1]    ldw        *S_R++,B5
;  ||[B1]    sub        B1, 1, B1
;
;            stw        B5,*D_R++
;  ||        sub        A1, 1, A1
;    [A1]    stw        B5,*D_R++
;  ||[A1]    sub        A1, 1, A1
;    [A1]    stw        B5,*D_R++
;  ||[A1]    sub        A1, 1, A1
;    [A1]    stw        B5,*D_R++
;  ||[A1]    sub        A1, 1, A1
;    [A1]    stw        B5,*D_R++
;  ||[A1]    sub        A1, 1, A1
;  
;    [B1]    b          Memcopy_loop                        
;            nop        5
;
;			B b3
;			NOP 5
;*************************************************************			 

			 
			 

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