main.c

TI DSP C6713 同相同公司C6414利用MSBSP多功能串口通讯的实例

#include <stdio.h>
#include <c6x.h>
#include <datatype.h>

#include <EDMA.h>
#include "regs.h"
#include "LINKPORT.h"
#include "timer.h"
#include "Msg_packet.h"


void EMIF_initiate();
void pll_int();
void Sports__Initialisation();
void RecMsgFromBaBu(MASTER_DATA_S *msg);
int  SendMsgToBaBu(SLAVE_DATA_S *msg);

MASTER_DATA_S	In_Packet;
SLAVE_DATA_S	Out_Packet;	

MASTER_DATA_S	In_Packet_Buddy;
SLAVE_DATA_S	Out_Packet_Buddy;

volatile int recv_done, recv_buddy_done, xmit_done;
int	rec_times , err_cnt, buddy_err_cnt;

void main (void)
{
	INT32S	i, j;
	
	pll_int();
	
	CSR=0x100;	        	       /* disable all interrupts            */
	IER=1;                           /* disable all interrupts except NMI */
	ICR=0xffff;                      /* clear all pending interrupts      */
	*(unsigned volatile int *)EERL = 0;
	*(unsigned volatile int *)CIERL = 0;

	edma_null_init();
	

    Sports__Initialisation();

    ICR = IFR | (1<<8);		//clear INT8 flag
    IER |= ((1<<8) + (1<<1));
    // enable int 8 (EDMA), and must sure that NMIE bit is enable.
    CSR |= 1;				// enable all interrupts CSR bit1 is GIE, it is Global interrupt enable bit; 

	

	Out_Packet.PacketHead = 0xABAB;
	rec_times = 0;	err_cnt = 0; buddy_err_cnt = 0;

	//0. prepare
	In_Packet.PacketHead = 0;
	In_Packet.Check_Sum  =  0xBEEF;	    
	recv_done = 0;
	RecMsgFromBaBu(&In_Packet);

	for(i = 1; i< 100000; i++)
	{
		//1. receive a msg from C64	
		while(!recv_done){;}
		rec_times++;

		if (In_Packet.Check_Sum 
			!= Msg_check_sum((unsigned short *)&In_Packet, PACKET_SIZE_IN_SHORT-1))
		{		err_cnt++;		}			

		Out_Packet.Target_x  = (i%128);		
		Out_Packet.Target_y  = (i%128);
		Out_Packet.State = 0;
		Out_Packet.Check_Sum  =  Msg_check_sum((unsigned short *)&Out_Packet, 
								PACKET_SIZE_IN_SHORT -1);

		//prepare the receive msg buffer for buddy communication
		Out_Packet_Buddy = Out_Packet;

		In_Packet_Buddy.PacketHead = 0;
		In_Packet_Buddy.Check_Sum  =  0xBEEF;	    
		RecMsgFromBuddy(&In_Packet_Buddy);
		recv_buddy_done = 0;
		
		//2. send a msg to buddy
		SendMsgToBuddy(&Out_Packet_Buddy);
		
		//3. receive a msg from buddy
		while(!recv_buddy_done){;}
		if (In_Packet_Buddy.Check_Sum 
			!= Msg_check_sum((unsigned short *)&In_Packet_Buddy, PACKET_SIZE_IN_SHORT-1))
		{		buddy_err_cnt++;		}
		
		//4. prepare the receive msg buffer and send a msg to C64			
		In_Packet.PacketHead = 0;
		In_Packet.Check_Sum  =  0xBEEF;	    
		recv_done = 0;
		RecMsgFromBaBu(&In_Packet);

		SendMsgToBaBu(&Out_Packet);
	}	
	
}


/*Define PLL Controller Registers */
#define	PLLPID		0x1B7C000	/*Peripheral identification register (PID)*/
// #define	PID_C6713	0x00010801	/*C6713 value: 0x00010801 for PLL Controller*/
#define	PLLCSR		0x1B7C100	/*PLL control/status register*/
#define	PLLM 		0x1B7C110	/*PLL multiplier control register*/
#define	PLLDIV0 	0x1B7C114	/*PLL controller divider 0 register*/
#define	PLLDIV1 	0x1B7C118	/*PLL controller divider 1 register*/
#define	PLLDIV2 	0x1B7C11c	/*PLL controller divider 2 register*/
#define	PLLDIV3 	0x1B7C120	/*PLL controller divider 3 register*/
#define	OSCDIV1 	0x1B7C124	/*Oscillator divider 1 register*/

#define	PLLCSR_BP	0x00		/* Bypass the PLL */
#define	PLLCSR_EP	0x01		/* Enable the PLL */
#define	PLLCSR_RST	0x08		/* Reset and disable the PLL */
#define	PLLM_INT	0x10		/* Initial Value for the PLL multiplier by *16 */
#define	PLLDIV0_INT	0x8000		/* Initial Value for the PLL Div0 by 1 */
#define	PLLDIV1_INT	0x8001		/* Initial Value for the PLL Div1 by 2 */
#define	PLLDIV2_INT	0x8003		/* Initial Value for the PLL Div2 by 4, it must be the half of SYSclk1 */
#define	PLLDIV3_INT	0x8003		/* Initial Value for the PLL Div3 by 4 */
#define	OSCDIV1_INT	0x8000		/* Initial Value for the OSC Div1 by 1 */


/****************************************************************************
    Data Type Definitions
****************************************************************************/
typedef unsigned int    DWORD;      /* 32-bit data type */
typedef unsigned short  WORD;       /* 16-bit data type */
typedef unsigned char   BYTE;       /* 8-bit data type */

void pll_int()
{	
	int i;
	*((volatile  WORD *)PLLCSR) = PLLCSR_BP;	//* Must enter Bypass mode first
	for(i=0;i<32;i++);	// Wait 4 cycles of the slowest of PLLOUT,
	
	*((volatile  WORD *)PLLCSR) = PLLCSR_RST;	//Reset and disable the PLL
	
	*((volatile  WORD *)PLLDIV0) = PLLDIV0_INT;	/* f=25M/1=25M*/
	*((volatile  WORD *)PLLM) = PLLM_INT;		/* f_pll=25M*16=400M */    
	*((volatile  WORD *)OSCDIV1) = OSCDIV1_INT; /* f_CLK3=25M/1=25M*/ 
	for(i=0;i<64;i++);	//Wait 8 cycles of the slowest of the old and new SYSCLK1-3 clock rates

	*((volatile  WORD *)PLLDIV3) = PLLDIV3_INT; /* f_ECLK=400M/4=100M*/  
	for(i=0;i<64;i++);	//Wait 8 cycles of the slowest of the old and new SYSCLK1-3 clock rates
	*((volatile  WORD *)PLLDIV2) = PLLDIV2_INT;	/* f_CLK2=400M/4=100M,must be the half of f_CORE */
	for(i=0;i<64;i++);	//Wait 8 cycles of the slowest of the old and new SYSCLK1-3 clock rates

	*((volatile  WORD *)PLLDIV1) = PLLDIV1_INT; /* f_CORE=400M/2=200M,must change after D1 when descend frequence*/      
	for (i=0;i<4096;i++);			//Wait for PLL to properly reset,512 CLKIN cycles
	*((volatile  WORD *)PLLCSR) = PLLCSR_BP;	/* Bring PLL out of reset */    
    	    									
	while ((*((volatile  WORD *)PLLCSR) & 0x40)==0)	; 	//Wait for PLL to lock, STABLE=1

	*((volatile  WORD *)PLLCSR) = PLLCSR_EP;	/* Enable inter PLL*/
	//*((volatile  WORD *)DEVCFG) = DEVCFG_INT; /* EMIF input clock source derive from SYSCLK3,The Default*/
}