📄 sport.c
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/*msg pingpong mechanism version
data: 2003/10
*/
#ifndef _SPORT_H_
#include "sport.h"
#endif
const unsigned char McBSPx_EDMA_Ch[3] = {12,14,17};
const unsigned char McBSPr_EDMA_Ch[3] = {13,15,18};
/*-------------------------------------------------------------------------*/
/* mcbsp_init() - */
/*-------------------------------------------------------------------------*/
/*
803VER20040420 old version
void mcbsp_init(unsigned int ch, unsigned int ClkGdv)
modefied by shiyan 2004/10/25
void mcbsp_init(unsigned int ch, unsigned int ClkGdv, unsigned int cnt)
cnt is the size in INT32 of the packet
*/
void mcbsp_init(unsigned int ch, unsigned int ClkGdv, unsigned int cnt)
{
int wait;
volatile McBSP_REG * mcbsp;
mcbsp = (volatile McBSP_REG *)(McBSP_BASE_ADDR(ch));
mcbsp->SPCR = 0; /* reset serial port */
/*********************************************************************************/
/*modefied by shiyan at 11/6/2003*/
mcbsp->SRGR = ((1<<CLKSM) + (0<<FSGM) +
(320<<FPER) + (ClkGdv<<CLKGDV));
// mcbsp->SRGR = ((1<<CLKSM) + (0<<FSGM) +
// ((ELEMENT_SIZE*MSG_SIZE-1)<<FPER) + (ClkGdv<<CLKGDV));
/*********************************************************************************/
mcbsp->PCR = ((1<<FSXM) + (1<<CLKXM)
+(0<<FSRM) + (0<<CLKRM));
// mcbsp->XCR = ((1<<FIG) + (5<<WDLEN1) +
// ((MSG_SIZE-1)<<FRLEN1) + (0<<DATDLY));
// mcbsp->RCR = ((1<<FIG) + (5<<WDLEN1) +
// ((MSG_SIZE-1)<<FRLEN1) + (0<<DATDLY));
mcbsp->XCR = ((1<<FIG) + (5<<WDLEN1) +
((cnt-1)<<FRLEN1) + (0<<DATDLY));
mcbsp->RCR = ((1<<FIG) + (5<<WDLEN1) +
((cnt-1)<<FRLEN1) + (0<<DATDLY));
mcbsp->MCR = 0;
mcbsp->SPCR |= (1<<GRST);
for (wait=0; wait<0x10; wait++);
mcbsp->SPCR |= ((1<<FREE)+(1<<FRST));
}
/*-------------------------------------------------------------------------*/
/* evt_edma_init() - used to initiate channel EDMA
read size 32bit from a FIFO to a ram */
/*modefied by shiyan at 11/6/2003*/
/*-------------------------------------------------------------------------*/
int SPORT_edmar_init(int dst, unsigned int MsBSP_ch, int size)
{
unsigned char DMA_ch;
volatile EDMA_REG *EDMA_reg ;
if((MsBSP_ch >= McBSP_CHANNEL_NUM))
return 0;
DMA_ch = McBSPr_EDMA_Ch[MsBSP_ch];
EDMA_reg = (volatile EDMA_REG *)EVENT_PARAMS_ADDR(DMA_ch);
*(unsigned volatile int *)ECRL |= (1<<DMA_ch); //Clear all pending events
//Config the EDMA Channel EDMA Transfer Parameters
EDMA_reg->opt = ((2<<PRI) + (0<<ESIZE) +
(0<<DS) + (0<<SUM) +
(0<<DD) + (1<<DUM) +
(1<<TCINT) + ((DMA_ch%16)<<TCC) + ((MsBSP_ch>>1)<<TCCM) +
(0<<LINK) + (0<<FS) );
EDMA_reg->src = SP_MEM_ADDR(MsBSP_ch);
EDMA_reg->cnt = size;
EDMA_reg->dst = dst;
EDMA_reg->idx = 0x00000000;
EDMA_reg->lnk = 0;
// EDMA_reg->lnk = ((0xffff& NULL_PARAMS_ADDR));
*(unsigned volatile int *)CIERL |= (1<<DMA_ch); //Enable EDMA Done INT
*(unsigned volatile int *)EERL |= (1<<DMA_ch); //only enable EVENT ch
return 1;
}
int SPORT_edmax_init(int src, unsigned int MsBSP_ch, int size)
{
unsigned char DMA_ch;
volatile EDMA_REG *EDMA_reg ;
if((MsBSP_ch >= McBSP_CHANNEL_NUM))
return 0;
DMA_ch = McBSPx_EDMA_Ch[MsBSP_ch];
EDMA_reg = (volatile EDMA_REG *)EVENT_PARAMS_ADDR(DMA_ch);
*(unsigned volatile int *)ECRL |= (1<<DMA_ch); //Clear all pending events
EDMA_reg->opt = ((2<<PRI) + (0<<ESIZE) +
(0<<DS) + (1<<SUM) +
(0<<DD) + (0<<DUM) +
(0<<TCINT) + ((DMA_ch%16)<<TCC) + ((MsBSP_ch>>1)<<TCCM) +
(1<<LINK) + (0<<FS) );
EDMA_reg->src = src;
EDMA_reg->cnt = size;
EDMA_reg->dst = SP_MEM_ADDR(MsBSP_ch);
EDMA_reg->idx = 0x00000000;
EDMA_reg->lnk = ((0xffff& NULL_PARAMS_ADDR));
*(unsigned volatile int *)EERL |= (1<<DMA_ch); //only enable EVENT ch
return 1;
}
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