c64_hw.c

TI DSP C6713 同相同公司C2812利用MSBSP多功能串口通讯的实例

#include <math.h>
#include <stdlib.h>
#include  "errormsg.h"

#include <SPORT.c>
#include <timer.c>
#include <Msg_tools.c>
#include <EDMA.c>
#include <datatype.h>
#include <EMIF.H>
#include "LINKPORT.h"
#include <Msg_packet.h>


extern volatile int recv_done, recv_buddy_done;

int  
SendMsgToBuddy(SLAVE_DATA_S *msg)
{
	RESET_BIT(McBSP_SPCR(BUDDY_BSPCH), XRST);
	if(!SPORT_edmax_init((int)msg, BUDDY_BSPCH, PACKET_SIZE_IN_INT))
		return -1;	
	SET_BIT(McBSP_SPCR(BUDDY_BSPCH), XRST);
		return 0;
}

void   
RecMsgFromBuddy(MASTER_DATA_S *msg)
{
	RESET_BIT(McBSP_SPCR(BUDDY_BSPCH), RRST);
	SPORT_edmar_init((int)msg, BUDDY_BSPCH, PACKET_SIZE_IN_INT);
	SET_BIT(McBSP_SPCR(BUDDY_BSPCH), RRST);	
}

int  
SendMsgToBaBu(SLAVE_DATA_S *msg)
{

	RESET_BIT(McBSP_SPCR(BABU_BSPCH), XRST);
	if(!SPORT_edmax_init((int)msg, BABU_BSPCH, PACKET_SIZE_IN_INT))
		return -1;	
	SET_BIT(McBSP_SPCR(BABU_BSPCH), XRST);
		return 0;
}

void   
RecMsgFromBaBu(MASTER_DATA_S *msg)
{
	RESET_BIT(McBSP_SPCR(BABU_BSPCH), RRST);
	SPORT_edmar_init((int)msg, BABU_BSPCH, PACKET_SIZE_IN_INT);
	SET_BIT(McBSP_SPCR(BABU_BSPCH), RRST);	
}

interrupt void edma_isr()
{
	if(GET_BIT(CIPRL, McBSPr_EDMA_Ch[BUDDY_BSPCH]))
	{
		REG_WRITE(CIPRL, (1<<McBSPr_EDMA_Ch[BUDDY_BSPCH]));
		recv_buddy_done=1;
	}
	else if(GET_BIT(CIPRL, McBSPr_EDMA_Ch[SPI_BSPCH]))
	{
		REG_WRITE(CIPRL, (1<<McBSPr_EDMA_Ch[SPI_BSPCH]));
		recv_done=1;
	}
}


void Sports__Initialisation()
{
	mcbsp_init(BUDDY_BSPCH, BUDDY_SPORT_ClkGdv, PACKET_SIZE_IN_INT);
}


/*
串口1工作在SPI模式,SPI初始化：串口1为Slave模式,工作时钟频率为10MHz.
*/
void SPI_McBSP1Slave_initial()
{
	short int wait=0;
	*(unsigned volatile int *)McBSP_SPCR(1) = 0x0;  /* reset serial port */
	*(unsigned volatile int *)McBSP_SRGR(1) = 0x20000000;  //0x20200000; 
// GSYNC   CLKSP    CLKSM    FSGM      FPER	  FWID	  CLKGDV
//  31       30       29      28     27 - 16 15 - 8   7 - 0  
//  0	      0	       1       0    	000    00	    00  
//GSYNC = 0: The sample rate generator clock (CLKG) is free running.
//CLKSP = 0: The rising edge of CLKS generates CLKG and FSG.
//CLKSM = 1: The sample rate generator clock is derived from the internal clock source.
//FSGM = 0: The transmit frame sync signal (FSX) is generated on every DXR-to-XSR copy.
//FPER = 0x20: Frame Period: FPER+1 CLKG : 33CLKG,32bit+1
//FWID = 0:	Frame width is FWID+1: 1 CLKG.
//CLKGDV = 0x9= 9 : so CLKG (baud rate) is (CPU/2)/(CLKGDV+1) = 100M/10 = 10M.

        *(unsigned volatile int *)McBSP_PCR(1) = 0x8; //0x0;      /* set pin control reg.  */ //此处从00H 改为0CH
//Reserved    XIOEN RIOEN FSXM FSRM CLKXM CLKRM Rsvd CLKS_STAT DX_STAT DR_STAT FSXP FSRP CLKXP CLKRP    
//31 - 14      13    12    11   10    9      8    7 	 6 	      5      4 	     3    2    1 	0
// 000          0    0     0     0    0      0    0	     0	      0      0       1    0	   0	0  
//FSXM = 0:Frame synchronization generation is provided by an external source.FSX is an input pin
//			rate generator frame synchronization mode bit FSGM in the SRGR.	
//CLKXM = 0:McBSP is a slave and (CLKX)is driven by the SPI Master in the system(During SPI mode).
        
        *(unsigned volatile int *)McBSP_RCR(1) = 0x40940;//0xA0;  /* set rx control reg. *///注意此处地RFIG可以为1
//RPHASE RFRLEN2 RWDLEN2 RCOMPAND RFIG RDATDLY	Rsvd RFRLEN1 RWDLEN1 RWDREVRS Rsvd
// 31    30 - 24 23 - 21 20 - 19   18  17 - 16   15  14 - 8   7 - 5     4     3 - 0
//  0	 0000000   000	   00	   1	  00	 0   0001001   010      0      0000
//RDATDLY = 00b: 0-bit data delay
//RPHASE = 0: Single phase frame
//RCOMPAND = 00b: No companding. Data transfer starts with MSB first.
//RDATDLY = 00: Receive data delay
//RFRLEN1 = 000 0000b: 1 word per phase
//RWDLEN1 = 101b: 32 bits

	*(unsigned volatile int *)McBSP_XCR(1) = 0x40940;//0xA0;  /* set tx control reg.   *///注意此处地RFIG

//XPHASE XFRLEN2 XWDLEN2 XCOMPAND XFIG XDATDLY	Rsvd XFRLEN1 XWDLEN1 XWDREVRS Rsvd
// 31    30 - 24 32 - 21 20 - 19   18  17 - 16   15  14 - 8   7 - 5     4     3 - 0
//  0	 0000000  000	   00	   1	  00	 0   0001001   010      0      0000		
//XDATDLY = 00b: 0-bit data delay
//XPHASE = 0: Single phase frame
//XCOMPAND = 00b: No companding. Data transfer starts with MSB first.
//XDATDLY = 00: Transfer data delay
//XFRLEN1 = 000 0000b: 1 word per phase
//XWDLEN1 = 101b: 32 bits
	*(unsigned volatile int *)McBSP_SPCR(1) |= 0x1000;	// CLKSTP=10

/*Rsvd    FREE	SOFT	FRST   GRST   XINTM    XSYNCERR XEMPTY XRDY XRST
 31 - 26   25    24      23     22   21 - 20       19     18    17   16
  000000   0	 0	      1      1       00	       0	   0	 0    0	
  	 
  DLB   RJUST   CLKSTP   Rsvd   DXENA Rsvd RINTM RSYNCERR RFULL RRDY RRST
  15   14 - 13 12 - 11  10 - 8    7     6  5 - 4    3      2      1    0  
   0	  00      10	  000	  1	    0    00	    0	   0	  0    0    */  
		
	*(unsigned volatile int *)McBSP_SPCR(1) |=0x400000; //0x0c00000;	//  GRST=1,FRST=1

/*Rsvd    FREE	SOFT	FRST   GRST   XINTM    XSYNCERR XEMPTY XRDY XRST
 31 - 26   25    24      23     22   21 - 20       19     18    17   16
  000000   0	 0	      0      1      00	        0	   0	 0    0	
  	 
  DLB   RJUST   CLKSTP   Rsvd   DXENA Rsvd RINTM RSYNCERR RFULL RRDY RRST
  15   14 - 13 12 - 11  10 - 8    7     6  5 - 4    3      2      1    0  
   0	  00      00	  000	  0	    0    00	    0	   0	  0    0    */

	  for (wait= 0; wait<8; wait++);

}

int evt_edmax_init(int src, int dst, int size, int ch)
{ 
#define EERL 0x01A0FFF4
#define ECRL 0x01A0FFF8
#define ESRL 0x01A0FFFC

	if((ch<0) || (ch >= EDMA_CHANNEL_NUM))
		return 0;
	

	//Config the EDMA Channel 	EDMA Transfer Parameters
//	*(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + OPT)= 0x41180002;
		//PRI ESIZE 2DS SUM 2DD DUM TCINT TCC  Reserved        LINK FS
		//010  00    0  01   0   00  1    1001 00000000000000  1    0

	*(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + OPT)= ((2<<PRI) + (1<<ESIZE)+
									(1<<SUM) + (0<<DUM) + (0 <<TCINT) + (ch<<TCC)+ 
									(((ch>16)? 1: 0) << TCCM ) + (1<<LINK) + (0<<FS));
	
	*(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + SRC)= src;
	*(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + CNT)= size;
	*(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + DST)= dst;
	*(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + IDX)= 0x00000000;
	*(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + LNK)= ((0xffff& NULL_PARAMS_ADDR));
	
//	*(unsigned volatile int *)CIERL |= (0 << ch);		//Enable EDMA Done INT 
	//Transfer complete code (TCCM+ :TCC) is 00 1001
	if(ch < 32)
		*(unsigned volatile int *)EERL |= (1 << ch);	//only enable EVENT ch
	else
		*(unsigned volatile int *)EERH |= (1 << (ch-32));	//only enable EVENT ch
	return 1;
}


/*-------------------------------------------------------------------------*/
/* evt_edma_init() - used to initiate channel  EDMA         
read from a FIFO to a ram                                                    */
/*-------------------------------------------------------------------------*/
int evt_edmar_init(int src, int dst, int size, int ch)
{ 

#define EERL 0x01A0FFF4
#define ECRL 0x01A0FFF8
#define ESRL 0x01A0FFFC

	if((ch<0) || (ch >= EDMA_CHANNEL_NUM))
		return 0;
	
	//Config the EDMA Channel 	EDMA Transfer Parameters
//	*(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + OPT)= 0x40390002;
		//PRI ESIZE 2DS SUM 2DD DUM TCINT TCC  Reserved        LINK FS
		//010  00    0  00   0   01  1    1000 00000000000000  1    0
	*(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + OPT)= ((2<<PRI) + (1<<ESIZE)+
									(0<<SUM) + (1<<DUM) + (1<<TCINT) + (ch<<TCC)+ 
									(((ch>16)? 1: 0) << TCCM ) + (1<<LINK) + (0<<FS));	//note

		
	*(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + SRC)= src;
	*(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + CNT)= size;
	*(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + DST)= dst;
	*(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + IDX)= 0x00000000;
	*(unsigned volatile int *)(EVENT_PARAMS_ADDR(ch) + LNK)= ((0xffff& NULL_PARAMS_ADDR));
	
	*(unsigned volatile int *)CIERL |= (1 << ch);		//Enable EDMA Done INT 
	//Transfer complete code (TCCM+ :TCC) is 00 1000
	if(ch < 32)
		*(unsigned volatile int *)EERL |= (1 << ch);	//only enable EVENT ch
	else
		*(unsigned volatile int *)EERH |= (1 << (ch-32));	//only enable EVENT ch
	return 1;
}