📄 f2812a.gel
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/********************************************************************/
/* Code Composer Studio supports five reserved GEL functions that */
/* automatically get executed if they are defined. They are: */
/* */
/* StartUp() - Executed whenever CCS is invoked */
/* OnReset() - Executed after Debug->Reset CPU */
/* OnRestart() - Executed after Debug->Restart */
/* OnPreFileLoaded() - Executed before File->Load Program */
/* OnFileLoaded() - Executed after File->Load Program */
/* */
/********************************************************************/
StartUp()
{
GEL_Halt(); /* Halt DSP */
GEL_Reset(); /* Reset DSP */
/* Initialize F2812 memory map */
F2812_Memory_Map();
Unlock_CSM();
Enable_DFT();
}
OnReset(int nErrorCode)
{
Unlock_CSM();
Enable_DFT();
}
/* uncomment the function(s) you want Code Composer Studio to execute
OnRestart(int nErrorCode)
{
}
OnPreFileLoaded()
{
}
OnFileLoaded(int nErrorCode, int bSymbolsOnly)
{
}
*/
menuitem "Initialize Memory Map";
/*------------------------ F2812 Memory Map ------------------------*/
/* */
/* Note: M0M1MAP and VMAP signals tied high on F2812 core */
/* */
/* 0x000000 - 0x0007ff M0/M1 SARAM (Prog and Data) */
/* 0x000800 - 0x000fff Peripheral Frame0 (PF0) (Data only) */
/* 0x002000 - 0x003fff XINTF ZONE 0 (Prog and Data) */
/* 0x004000 - 0x005fff XINTF ZONE 1 (Prog and Data) */
/* 0x006000 - 0x006fff Peripheral Frame1 (PF1) (Data only) */
/* 0x007000 - 0x007fff Peripheral Frame2 (PF2) (Data only) */
/* 0x008000 - 0x009fff L0/L1 SARAM (Prog and Data) */
/* 0x080000 - 0x0fffff XINTF ZONE 2 (Prog and Data) */
/* 0x100000 - 0x17ffff XINTF ZONE 6 (Prog and Data) */
/* 0x3d7800 - 0x3d7fff OTP (Prog and Data) */
/* 0x3d8000 - 0x3f7fff FLASH (Prog and Data) */
/* 0x3f8000 - 0x3f9fff H0 SARAM (Prog and Data) */
/* 0x3fc000 - 0x3fffff XINTF ZONE 7 (MPNMC=1) (Prog and Data) */
/* 0x3ff000 - 0x3fffff BOOT ROM (MPNMC=0) (Prog and Data) */
/*------------------------------------------------------------------*/
hotmenu F2812_Memory_Map()
{
int XINTCNF2 = *0xb34; /* XINT Configuration Register 2 */
GEL_MapReset();
GEL_MapOn();
/* Program memory maps */
GEL_MapAdd(0x0,0,0x800,1,1); /* M0/M1 SARAM */
GEL_MapAdd(0x2000,0,0x2000,1,1); /* XINTF ZONE 0 */
GEL_MapAdd(0x4000,0,0x2000,1,1); /* XINTF ZONE 1 */
GEL_MapAdd(0x8000,0,0x2000,1,1); /* L0/L1 SARAM */
GEL_MapAdd(0x80000,0,0x80000,1,1); /* XINTF ZONE 2 */
GEL_MapAdd(0x100000,0,0x80000,1,1); /* XINTF ZONE 6 */
GEL_MapAdd(0x3d7800,0,0x800,1,0); /* OTP */
GEL_MapAdd(0x3d8000,0,0x20000,1,0); /* FLASH */
GEL_MapAdd(0x3f8000,0,0x2000,1,1); /* H0 SARAM */
/* Data memory maps */
GEL_MapAdd(0x0,1,0x800,1,1); /* M0/M1 SARAM */
GEL_MapAdd(0x800,1,0x800,1,1); /* PF0 */
GEL_MapAdd(0x2000,1,0x2000,1,1); /* XINTF ZONE 0 */
GEL_MapAdd(0x4000,1,0x2000,1,1); /* XINTF ZONE 1 */
GEL_MapAdd(0x6000,1,0x1000,1,1); /* PF1 */
GEL_MapAddStr(0x7000,1,0x1000,"R|W|AS2",0); /* PF2 */
GEL_MapAdd(0x8000,1,0x2000,1,1); /* L0/L1 SARAM */
GEL_MapAdd(0x80000,1,0x80000,1,1); /* XINTF ZONE 2 */
GEL_MapAdd(0x100000,1,0x80000,1,1); /* XINTF ZONE 6 */
GEL_MapAdd(0x3d7800,1,0x800,1,0); /* OTP */
GEL_MapAdd(0x3d8000,1,0x20000,1,0); /* FLASH */
GEL_MapAdd(0x3f8000,1,0x2000,1,1); /* H0 SARAM */
/* Check MPNMC value (XINTCNF2 bit 8) to determine map setting. */
if(XINTCNF2 & 0x100)
{ /* Map External Interface Zone 7 if MPNMC = 1 */
GEL_MapAdd(0x3fc000,0,0x4000,1,1); /* XINTF ZONE 7 */
GEL_MapAdd(0x3fc000,1,0x4000,1,1); /* XINTF ZONE 7 */
}
else
{ /* Map Boot ROM if MPNMC = 0 */
GEL_MapAdd(0x3ff000,0,0x1000,1,0); /* BOOT ROM */
GEL_MapAdd(0x3ff000,1,0x1000,1,0); /* BOOT ROM */
}
}
/* Enable DFT read/write for SARAM blocks */
Enable_DFT()
{
*0x950 = 0x0300; /* M0 */
*0x951 = 0x0300; /* M1 */
*0x952 = 0x0300; /* L0 */
*0x953 = 0x0300; /* L1 */
*0x954 = 0x0300; /* H0 */
}
menuitem "Watchdog";
hotmenu Disable_WD()
{
/* Enable WD override */
*0x7029 = *0x7029 | 0x0068;
*0x7025 = 0x0055;
*0x7025 = 0x00AA;
}
menuitem "Code Security Module"
hotmenu Unlock_CSM()
{
/* Read the password locations */
XAR0 = *0x3F7FF8;
XAR0 = *0x3F7FF9;
XAR0 = *0x3F7FFA;
XAR0 = *0x3F7FFB;
XAR0 = *0x3F7FFC;
XAR0 = *0x3F7FFD;
XAR0 = *0x3F7FFE;
XAR0 = *0x3F7FFF;
/* Assumes flash is erased */
*0xAE0 = 0xFFFF;
*0xAE1 = 0xFFFF;
*0xAE2 = 0xFFFF;
*0xAE3 = 0xFFFF;
*0xAE4 = 0xFFFF;
*0xAE5 = 0xFFFF;
*0xAE6 = 0xFFFF;
*0xAE7 = 0xFFFF;
}
menuitem "Addressing Modes";
hotmenu C27x_Mode()
{
AMODE = 0;
OBJMODE = 0;
}
hotmenu C28x_Mode()
{
AMODE = 0;
OBJMODE = 1;
}
hotmenu C2xLP_Mode()
{
AMODE = 1;
OBJMODE = 1;
}
/*--------------------------- PLL Ratios ---------------------------*/
/* The following table describes the PLL clocking ratios (0..10) */
/* that are supported if XF_XPLLDIS = 1. */
/* */
/* Ratio CLKIN Description */
/* ----- -------------- ------------ */
/* 0 OSCCLK/2 PLL bypassed */
/* 1 (OSCCLK * 1)/2 15 Mhz for 30 Mhz CLKIN */
/* 2 (OSCCLK * 2)/2 30 Mhz for 30 Mhz CLKIN */
/* 3 (OSCCLK * 3)/2 45 Mhz for 30 Mhz CLKIN */
/* 4 (OSCCLK * 4)/2 60 Mhz for 30 Mhz CLKIN */
/* 5 (OSCCLK * 5)/2 75 Mhz for 30 Mhz CLKIN */
/* 6 (OSCCLK * 6)/2 90 Mhz for 30 Mhz CLKIN */
/* 7 (OSCCLK * 7)/2 105 Mhz for 30 Mhz CLKIN */
/* 8 (OSCCLK * 8)/2 120 Mhz for 30 Mhz CLKIN */
/* 9 (OSCCLK * 9)/2 135 Mhz for 30 Mhz CLKIN */
/* 10 (OSCCLK * 10)/2 150 Mhz for 30 Mhz CLKIN */
/********************************************************************/
menuitem "Set PLL Ratio";
hotmenu Bypass()
{
*0x7021 = 0; /* CLKIN = OSCCLK/2, PLL is bypassed */
PLL_Wait();
}
hotmenu OSCCLK_x1()
{
*0x7021 = 1; /* CLKIN = (OSCCLK * 1)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x2()
{
*0x7021 = 2; /* CLKIN = (OSCCLK * 2)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x3()
{
*0x7021 = 3; /* CLKIN = (OSCCLK * 3)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x4()
{
*0x7021 = 4; /* CLKIN = (OSCCLK * 4)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x5()
{
*0x7021 = 5; /* CLKIN = (OSCCLK * 5)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x6()
{
*0x7021 = 6; /* CLKIN = (OSCCLK * 6)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x7()
{
*0x7021 = 7; /* CLKIN = (OSCCLK * 7)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x8()
{
*0x7021 = 8; /* CLKIN = (OSCCLK * 8)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x9()
{
*0x7021 = 9; /* CLKIN = (OSCCLK * 9)/2 */
PLL_Wait();
}
hotmenu OSCCLK_x10()
{
*0x7021 = 10; /* CLKIN = (OSCCLK * 10)/2 */
PLL_Wait();
}
PLL_Wait()
{
int delay = 0;
/* Minimum delay for PLL lock is 4096 OSCCLKs cycles. Wait loop */
/* may need adjusted depending on speed of host PC. */
while (delay < 10000)
{
delay += 1;
}
}
/********************************************************************/
/* This GEL file is used to display the symbolic names of the f2812 */
/* memory mapped registers in the watch window. To view these */
/* registers, click on the GEL menu button in Code Composer Studio, */
/* then select which registers or groups of registers you want to */
/* view. They will appear in the watch window under the Watch1 tab. */
/********************************************************************/
/* Add a space line to the GEL menu */
menuitem "______________________________________";
hotmenu _() {}
/********************************************************************/
/* A/D Converter Registers */
/********************************************************************/
menuitem "Watch ADC Registers";
hotmenu All_ADC_Regs()
{
GEL_WatchAdd("*0x7100,x","ADCTRL1");
GEL_WatchAdd("*0x7101,x","ADCTRL2");
GEL_WatchAdd("*0x7102,x","ADCMAXCONV");
GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1");
GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2");
GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3");
GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4");
GEL_WatchAdd("*0x7107,x","ADCASEQSR");
GEL_WatchAdd("*0x7108,x","ADCRESULT0");
GEL_WatchAdd("*0x7109,x","ADCRESULT1");
GEL_WatchAdd("*0x710A,x","ADCRESULT2");
GEL_WatchAdd("*0x710B,x","ADCRESULT3");
GEL_WatchAdd("*0x710C,x","ADCRESULT4");
GEL_WatchAdd("*0x710D,x","ADCRESULT5");
GEL_WatchAdd("*0x710E,x","ADCRESULT6");
GEL_WatchAdd("*0x710F,x","ADCRESULT7");
GEL_WatchAdd("*0x7110,x","ADCRESULT8");
GEL_WatchAdd("*0x7111,x","ADCRESULT9");
GEL_WatchAdd("*0x7112,x","ADCRESULT10");
GEL_WatchAdd("*0x7113,x","ADCRESULT11");
GEL_WatchAdd("*0x7114,x","ADCRESULT12");
GEL_WatchAdd("*0x7115,x","ADCRESULT13");
GEL_WatchAdd("*0x7116,x","ADCRESULT14");
GEL_WatchAdd("*0x7117,x","ADCRESULT15");
GEL_WatchAdd("*0x7118,x","ADCTRL3");
GEL_WatchAdd("*0x7119,x","ADCST");
}
hotmenu ADCTRL1()
{
GEL_WatchAdd("*0x7100,x","ADCTRL1");
}
hotmenu ADCTRL2()
{
GEL_WatchAdd("*0x7101,x","ADCTRL2");
}
hotmenu ADCMAXCONV()
{
GEL_WatchAdd("*0x7102,x","ADCMAXCONV");
}
hotmenu ADCCHSELSEQx_Regs()
{
GEL_WatchAdd("*0x7103,x","ADCCHSELSEQ1");
GEL_WatchAdd("*0x7104,x","ADCCHSELSEQ2");
GEL_WatchAdd("*0x7105,x","ADCCHSELSEQ3");
GEL_WatchAdd("*0x7106,x","ADCCHSELSEQ4");
}
hotmenu ADCASEQSR()
{
GEL_WatchAdd("*0x7107,x","ADCASEQSR");
}
hotmenu ADCRESULT_0_to_3()
{
GEL_WatchAdd("*0x7108,x","ADCRESULT0");
GEL_WatchAdd("*0x7109,x","ADCRESULT1");
GEL_WatchAdd("*0x710A,x","ADCRESULT2");
GEL_WatchAdd("*0x710B,x","ADCRESULT3");
}
hotmenu ADCRESULT_4_to_7()
{
GEL_WatchAdd("*0x710C,x","ADCRESULT4");
GEL_WatchAdd("*0x710D,x","ADCRESULT5");
GEL_WatchAdd("*0x710E,x","ADCRESULT6");
GEL_WatchAdd("*0x710F,x","ADCRESULT7");
}
hotmenu ADCRESULT_8_to_11()
{
GEL_WatchAdd("*0x7110,x","ADCRESULT8");
GEL_WatchAdd("*0x7111,x","ADCRESULT9");
GEL_WatchAdd("*0x7112,x","ADCRESULT10");
GEL_WatchAdd("*0x7113,x","ADCRESULT11");
}
hotmenu ADCRESULT_12_to_15()
{
GEL_WatchAdd("*0x7114,x","ADCRESULT12");
GEL_WatchAdd("*0x7115,x","ADCRESULT13");
GEL_WatchAdd("*0x7116,x","ADCRESULT14");
GEL_WatchAdd("*0x7117,x","ADCRESULT15");
}
hotmenu ADCCTRL3()
{
GEL_WatchAdd("*0x7118,x","ADCTRL3");
}
hotmenu ADCST()
{
GEL_WatchAdd("*0x7119,x","ADCST");
}
/********************************************************************/
/* Clocking and Low-Power Registers */
/********************************************************************/
menuitem "Watch Clocking and Low-Power Registers";
hotmenu All_Clocking_and_Low_Power_Regs()
{
GEL_WatchAdd("*0x701A,x","HISPCP");
GEL_WatchAdd("*0x701B,x","LOSPCP");
GEL_WatchAdd("*0x701C,x","PCLKCR");
GEL_WatchAdd("*0x701E,x","LPMCR0");
GEL_WatchAdd("*0x701F,x","LPMCR1");
GEL_WatchAdd("*0x7021,x","PLLCR");
}
hotmenu HISPCP()
{
GEL_WatchAdd("*0x701A,x","HISPCP");
}
hotmenu LOSPCP()
{
GEL_WatchAdd("*0x701B,x","LOSPCP");
}
hotmenu PCLKCR()
{
GEL_WatchAdd("*0x701C,x","PCLKCR");
}
hotmenu LPMCR0()
{
GEL_WatchAdd("*0x701E,x","LPMCR0");
}
hotmenu LPMCR1()
{
GEL_WatchAdd("*0x701F,x","LPMCR1");
}
hotmenu PLLCR()
{
GEL_WatchAdd("*0x7021,x","PLLCR");
}
/********************************************************************/
/* Code Security Module Registers */
/********************************************************************/
menuitem "Watch Code Security Module Registers";
hotmenu CSMSCR()
{
GEL_WatchAdd("*0x0AEF,x","CSMSCR");
GEL_WatchAdd("(*0x0AEF>>15)&1,d"," FORCESEC bit");
GEL_WatchAdd("(*0x0AEF)&1,d"," SECURE bit");
}
hotmenu PWL_Locations()
{
GEL_WatchAdd("*0x3F7FF8,x","PWL0");
GEL_WatchAdd("*0x3F7FF9,x","PWL1");
GEL_WatchAdd("*0x3F7FFA,x","PWL2");
GEL_WatchAdd("*0x3F7FFB,x","PWL3");
GEL_WatchAdd("*0x3F7FFC,x","PWL4");
GEL_WatchAdd("*0x3F7FFD,x","PWL5");
GEL_WatchAdd("*0x3F7FFE,x","PWL6");
GEL_WatchAdd("*0x3F7FFF,x","PWL7");
}
/********************************************************************/
/* CPU Timer Registers */
/********************************************************************/
menuitem "Watch CPU Timer Registers";
hotmenu All_CPU_Timer0_Regs()
{
GEL_WatchAdd("*0x0C00,x","TIMER0TIM");
GEL_WatchAdd("*0x0C01,x","TIMER0TIMH");
GEL_WatchAdd("*0x0C02,x","TIMER0PRD");
GEL_WatchAdd("*0x0C03,x","TIMER0PRDH");
GEL_WatchAdd("*0x0C04,x","TIMER0TCR");
GEL_WatchAdd("*0x0C06,x","TIMER0TPR");
GEL_WatchAdd("*0x0C07,x","TIMER0TPRH");
}
hotmenu All_CPU_Timer1_Regs()
{
GEL_WatchAdd("*0x0C08,x","TIMER1TIM");
GEL_WatchAdd("*0x0C09,x","TIMER1TIMH");
GEL_WatchAdd("*0x0C0A,x","TIMER1PRD");
GEL_WatchAdd("*0x0C0B,x","TIMER1PRDH");
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