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GAS LISTING /tmp/cc60KWFF.s page 1 1 # 1 "BootloaderBsp/start.S" 2 # 1 "/home/zzxiong/osek//" 1 /*
1 ... 0 0 2 * File: start.S
3 *
4 * Discription: startup code
5 *
6 */
7
8 #include "board_mpc555.h"
1 /*
2 * File: board_mpc555.h
3 *
4 * Discription: Config header file for XXX
5 * board using an MPC555 CPU
6 *We should kown the configuration of the board in order to write this file.
7 */
8
9 #ifndef __BOARD_MPC555_H__
10 #define __BOARD_MPC555_H__
11
12 /* Internal Memory Mapped (This is not the IMMR content)*/
13 #define CFG_IMMR 0x00000000 /* Physical start adress of internal memory map */
14
15 #define init_end 0x0 /*end of initialization*/
16
17 /* Definitions for initial stack pointer and data area*/
18 #define CFG_INIT_RAM_ADDR (CFG_IMMR + 0x003f9800) /* Physical start adress of internal MPC55 19 #define CFG_INIT_RAM_END (CFG_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 20 #define CFG_GBL_DATA_SIZE 64 /* Size in bytes reserved for initial global data */
21 #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_INIT_RAM_ADDR) - CFG_GBL_DATA_SIZE) /* Offset 22 //#define CFG_INIT_SP_ADDR 0x013fa000 /* Physical start adress of inital stack */
23 24 /*MPC555 10K of internal SRAM A used for stack*/
25 /*Stack Address Parameters*/
26
27 #define __SP_INIT 0x00400000
28 #define __STACK_SIZE 0x2800
29 #define __SP_END (__SP_INIT - __STACK_SIZE)
30 /*
31 * Start addresses for the final memory configuration
32 * Please note that CFG_SDRAM_BASE _must_ start at 0
33 */
34 #define EXTERNAL_RAM 0x0 /*Whether have external ram*/
35 #define CFG_SDRAM_BASE 0x00000000 /* External RAM base address */
36 #define CFG_SDRAM_SIZE 0x0 /*External RAM size*/
37 #define CFG_STACK_SIZE 0x0 /*stack size in sdram, used by exception and OS*/
38 #define CFG_FLASH_BASE 0x00000000 /* External flash */
39
9 #include "mpc555.h"
1 /*
2 * File: mpc555.h
3 *
4 * Discription: mpc5xx specific definitions
GAS LISTING /tmp/cc60KWFF.s page 2 5 *
6 */
7
8 #ifndef __MPC555_H__
9 #define __MPC555_H__
10
11 /*-----------------------------------------------------------------------
12 * Exception offsets (PowerPC standard)
13 */
14 #define EXC_OFF_SYS_RESET 0x0100 /* System reset */
15
16 /*-----------------------------------------------------------------------
17 * IMMR(internal memory map register)
18 */
19 #define IMMR_ISB 0x00000000
20 #define IMMR_FLEN 0x00000800 //启动是从外部FLASH还是从片上FLASH开始
21 #define CFG_IMMR_SET (IMMR_ISB | IMMR_FLEN)
22
23 /*-----------------------------------------------------------------------
24 * MSR (machine status register)
25 */
26 #define MSR_EE 0x00000000 //是否允许外部中断
27 #define MSR_FP 0x00000000 //是否使用浮点功能
28 #define MSR_ME 0x00000000 //是否允许机器检测异常
29 #define MSR_RI 0x00000000 //机器状态是否可恢复
30 #define MSR_LE 0x00000000 //采用小顶端还是大顶端模式
31 #define CFG_MSR (MSR_EE | MSR_FP | MSR_ME | MSR_RI | MSR_LE)
32
33 /*-----------------------------------------------------------------------
34 * BBCMCR(bbc module configuration register)
35 */
36 #define BBCMCR_OERC 0x00000000 //other exceptions relocation control
37 #define BBCMCR_ETRE 0x00000000 //exception table relocation enable
38 #define CFG_BBCMCR (BBCMCR_OERC | BBCMCR_ETRE)
39
40 /*-----------------------------------------------------------------------
41 * SYPCR - System Protection Control Register
42 */
43 #define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count */
44 #define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */
45 #define SYPCR_BME 0x00000080 /* Bus Monitor Enable */
46 #define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */
47 #define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */
48 #define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */
49 #define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */
50 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI| SYPCR_ 51
52
53 /*-----------------------------------------------------------------------
54 * SIUMCR - SIU Module Configuration Register
55 */
56 #define SIUMCR_EARB 0x80000000 /* External Arbitration */
57 #define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */
58 #define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */
59 #define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */
60 #define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */
61 #define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */
GAS LISTING /tmp/cc60KWFF.s page 3 62 #define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */
63 #define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */
64 #define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */
65 #define SIUMCR_DSHW 0x00800000 /* Data Showcycles */
66 #define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */
67 #define SIUMCR_DBGC01 0x00200000 /* - " - */
68 #define SIUMCR_DBGC10 0x00400000 /* - " - */
69 #define SIUMCR_DBGC11 0x00600000 /* - " - */
70 #define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */
71 #define SIUMCR_DBPC01 0x00080000 /* - " - */
72 #define SIUMCR_DBPC10 0x00100000 /* - " - */
73 #define SIUMCR_DBPC11 0x00180000 /* - " - */
74 #define SIUMCR_GPC00 0x00000000 /* General Pins Config */
75 #define SIUMCR_GPC01 0x00020000 /* General Pins Config */
76 #define SIUMCR_GPC10 0x00040000 /* General Pins Config */
77 #define SIUMCR_GPC11 0x00060000 /* General Pins Config */
78 #define SIUMCR_DLK 0x00010000 /* Debug Register Lock */
79 #define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */
80 #define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */
81 #define SIUMCR_SC10 0x00004000 /* Single adress show */
82 #define SIUMCR_SC11 0x00006000 /* Single adress */
83 #define SIUMCR_RCTX 0x00001000 /* Data Parity pins Config. */
84 #define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */
85 #define SIUMCR_MLRC01 0x00000400 /* - " - */
86 #define SIUMCR_MLRC10 0x00000800 /* - " - */
87 #define SIUMCR_MLRC11 0x00000c00 /* - " - */
88 #define SIUMCR_MTSC 0x00000100 /* Memory transfer */
89 #define CFG_SIUMCR (SIUMCR_SC11)
90
91 /*-----------------------------------------------------------------------
92 * TBSCR - Time Base Status and Control Register
93 */
94 #define TBSCR_REFA ((ushort)0x0080) /* Reference Interrupt Status A */
95 #define TBSCR_REFB ((ushort)0x0040) /* Reference Interrupt Status B */
96 #define TBSCR_TBF ((ushort)0x0002) /* Time Base stops while FREEZE */
97 #define TBSCR_TBE ((ushort)0x0001) /*Time Base enables*/
98 #define CFG_TBSCR ()
99
100 /*-----------------------------------------------------------------------
101 * PISCR - Periodic Interrupt Status and Control Register
102 */
103 #define PISCR_PITF ((ushort)0x0002) /* PIT stops when FREEZE */
104 #define PISCR_PS 0x0080 /* Periodic Interrupt Status */
105 #define CFG_PISCR ()
106
107 /*-----------------------------------------------------------------------
108 * PLPRCR - PLL, Low-Power, and Reset Control Register
109 */
110 #define PLPRCR_MF_MSK 0xfff00000 /* MF mask */
111 #define PLPRCR_DIVF_MSK 0x0000001f /* DIVF mask */
112 #define PLPRCR_CSRC_MSK 0x00000400 /* CSRC mask */
113 #define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */
114 #define PLPRCR_DIVF_0 0x00000000 /* Division factor 0 */
115 #define PLPRCR_MF_9 0x00900000 /* Mulitipliaction factor 9 */
116 #define PLPRCR_TEXPS 0x00004000 /* TEXP Status */
117 #define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */
118 #define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */
GAS LISTING /tmp/cc60KWFF.s page 4 119 #define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */
120 #define CFG_PLPRCR ()
121
122 /*-----------------------------------------------------------------------
123 * SCCR - System Clock and reset Control Register
124 */
125 #define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */
126 #define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */
127 #define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */
128 #define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */
129 #define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */
130 #define SCCR_EBDF11 0x00060000 /* reserved */
131 #define SCCR_TBS 0x02000000 /* Time Base Source */
132 #define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
133 #define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */
134 #define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */
135 #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
136 #define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */
137 #define SCCR (0x00000000)
138
139 /*-----------------------------------------------------------------------
140 * MC - Memory Controller
141 */
142 #define BR_V 0x00000001 /* Bank valid */
143 #define BR_BI 0x00000002 /* Burst inhibit */
144 #define BR_PS_8 0x00000400 /* 8 bit port size */
145 #define BR_PS_16 0x00000800 /* 16 bit port size */
146 #define BR_PS_32 0x00000000 /* 32 bit port size */
147 #define BR_LBDIR 0x00000008 /* Late burst data in progess */
148 #define BR_SETA 0x00000004 /* External Data Acknowledge */
149 #define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */
150 #define OR_SCY_1 0x00000000 /* 1 clock cycle wait state */
151 #define OR_SCY_8 0x00000080 /* 8 clock cycles wait states */
152 #define OR_TRLX 0x00000001 /* Timing relaxed */
153 #define OR_BSCY 0x00000060 /* Burst beats length in clocks */
154 #define OR_ACS_10 0x00000600 /* Adress to chip-select setup */
155 #define OR_CSNT 0x00000800 /* Chip-select negotation time */
156 #define OR_ETHR 0x00000100 /* Extended hold time on read */
157 #define OR_ADDR_MK_FF 0xFF000000
158 #define OR_ADDR_MK_FFFF 0xFFFF0000
159
160 /*-----------------------------------------------------------------------
161 * UMCR - UIMB Module Configuration Register
162 */
163 #define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */
164 #define UMCR_HSPEED 0x10000000 /* Half speed */
165 #define CFG_UMCR (UMCR_FSPEED)
166
167 /*-----------------------------------------------------------------------
168 * DER - Timer Decrementer
169 *-----------------------------------------------------------------------
170 * Initialise to zero
171 */
172 #define CFG_DER 0x00000000
173
174
175 /* The key to unlock registers maintained by keep-alive power.
GAS LISTING /tmp/cc60KWFF.s page 5 176 */
177 #define KAPWR_KEY 0x55ccaa33
178
10 #include "ppc_asm.h"
1 /*
2 * This file contains all the macros and symbols which define
3 * a PowerPC assembly language environment.
4 */
5
6 #ifndef __PPC_ASM_TMPL__
7 #define __PPC_ASM_TMPL__
8
9 /***************************************************************************
10 * Register names
11 */
12 #define r0 0
13 #define r1 1
14 #define r2 2
15 #define r3 3
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