translate.c.svn-base

我们自己开发的一个OSEK操作系统！不知道可不可以？

        case 0x37:
            /* PKLB */
            if (!(ctx->amask & AMASK_MVI))
                goto invalid_opc;
            /* XXX: TODO */
            goto invalid_opc;
            break;
        case 0x38:
            /* MINSB8 */
            if (!(ctx->amask & AMASK_MVI))
                goto invalid_opc;
            /* XXX: TODO */
            goto invalid_opc;
            break;
        case 0x39:
            /* MINSW4 */
            if (!(ctx->amask & AMASK_MVI))
                goto invalid_opc;
            /* XXX: TODO */
            goto invalid_opc;
            break;
        case 0x3A:
            /* MINUB8 */
            if (!(ctx->amask & AMASK_MVI))
                goto invalid_opc;
            /* XXX: TODO */
            goto invalid_opc;
            break;
        case 0x3B:
            /* MINUW4 */
            if (!(ctx->amask & AMASK_MVI))
                goto invalid_opc;
            /* XXX: TODO */
            goto invalid_opc;
            break;
        case 0x3C:
            /* MAXUB8 */
            if (!(ctx->amask & AMASK_MVI))
                goto invalid_opc;
            /* XXX: TODO */
            goto invalid_opc;
            break;
        case 0x3D:
            /* MAXUW4 */
            if (!(ctx->amask & AMASK_MVI))
                goto invalid_opc;
            /* XXX: TODO */
            goto invalid_opc;
            break;
        case 0x3E:
            /* MAXSB8 */
            if (!(ctx->amask & AMASK_MVI))
                goto invalid_opc;
            /* XXX: TODO */
            goto invalid_opc;
            break;
        case 0x3F:
            /* MAXSW4 */
            if (!(ctx->amask & AMASK_MVI))
                goto invalid_opc;
            /* XXX: TODO */
            goto invalid_opc;
            break;
        case 0x70:
            /* FTOIT */
            if (!(ctx->amask & AMASK_FIX))
                goto invalid_opc;
            gen_fti(ctx, &gen_op_ftoit, ra, rb);
            break;
        case 0x78:
            /* FTOIS */
            if (!(ctx->amask & AMASK_FIX))
                goto invalid_opc;
            gen_fti(ctx, &gen_op_ftois, ra, rb);
            break;
        default:
            goto invalid_opc;
        }
        break;
    case 0x1D:
        /* HW_MTPR (PALcode) */
#if defined (CONFIG_USER_ONLY)
        goto invalid_opc;
#else
        if (!ctx->pal_mode)
            goto invalid_opc;
        gen_load_ir(ctx, ra, 0);
        gen_op_mtpr(insn & 0xFF);
        ret = 2;
        break;
#endif
    case 0x1E:
        /* HW_REI (PALcode) */
#if defined (CONFIG_USER_ONLY)
        goto invalid_opc;
#else
        if (!ctx->pal_mode)
            goto invalid_opc;
        if (rb == 31) {
            /* "Old" alpha */
            gen_op_hw_rei();
        } else {
            gen_load_ir(ctx, rb, 0);
            gen_set_uT1(ctx, (((int64_t)insn << 51) >> 51));
            gen_op_addq();
            gen_op_hw_ret();
        }
        ret = 2;
        break;
#endif
    case 0x1F:
        /* HW_ST (PALcode) */
#if defined (CONFIG_USER_ONLY)
        goto invalid_opc;
#else
        if (!ctx->pal_mode)
            goto invalid_opc;
        gen_load_ir(ctx, rb, 0);
        gen_set_sT1(ctx, disp12);
        gen_op_addq();
        gen_load_ir(ctx, ra, 1);
        switch ((insn >> 12) & 0xF) {
        case 0x0:
            /* Longword physical access */
            gen_op_stl_raw();
            break;
        case 0x1:
            /* Quadword physical access */
            gen_op_stq_raw();
            break;
        case 0x2:
            /* Longword physical access with lock */
            gen_op_stl_c_raw();
            break;
        case 0x3:
            /* Quadword physical access with lock */
            gen_op_stq_c_raw();
            break;
        case 0x4:
            /* Longword virtual access */
            gen_op_st_phys_to_virt();
            gen_op_stl_raw();
            break;
        case 0x5:
            /* Quadword virtual access */
            gen_op_st_phys_to_virt();
            gen_op_stq_raw();
            break;
        case 0x6:
            /* Invalid */
            goto invalid_opc;
        case 0x7:
            /* Invalid */
            goto invalid_opc;
        case 0x8:
            /* Invalid */
            goto invalid_opc;
        case 0x9:
            /* Invalid */
            goto invalid_opc;
        case 0xA:
            /* Invalid */
            goto invalid_opc;
        case 0xB:
            /* Invalid */
            goto invalid_opc;
        case 0xC:
            /* Longword virtual access with alternate access mode */
            gen_op_set_alt_mode();
            gen_op_st_phys_to_virt();
            gen_op_ldl_raw();
            gen_op_restore_mode();
            break;
        case 0xD:
            /* Quadword virtual access with alternate access mode */
            gen_op_set_alt_mode();
            gen_op_st_phys_to_virt();
            gen_op_ldq_raw();
            gen_op_restore_mode();
            break;
        case 0xE:
            /* Invalid */
            goto invalid_opc;
        case 0xF:
            /* Invalid */
            goto invalid_opc;
        }
        ret = 2;
        break;
#endif
    case 0x20:
        /* LDF */
#if 0 // TODO
        gen_load_fmem(ctx, &gen_ldf, ra, rb, disp16);
#else
        goto invalid_opc;
#endif
        break;
    case 0x21:
        /* LDG */
#if 0 // TODO
        gen_load_fmem(ctx, &gen_ldg, ra, rb, disp16);
#else
        goto invalid_opc;
#endif
        break;
    case 0x22:
        /* LDS */
        gen_load_fmem(ctx, &gen_lds, ra, rb, disp16);
        break;
    case 0x23:
        /* LDT */
        gen_load_fmem(ctx, &gen_ldt, ra, rb, disp16);
        break;
    case 0x24:
        /* STF */
#if 0 // TODO
        gen_store_fmem(ctx, &gen_stf, ra, rb, disp16);
#else
        goto invalid_opc;
#endif
        break;
    case 0x25:
        /* STG */
#if 0 // TODO
        gen_store_fmem(ctx, &gen_stg, ra, rb, disp16);
#else
        goto invalid_opc;
#endif
        break;
    case 0x26:
        /* STS */
        gen_store_fmem(ctx, &gen_sts, ra, rb, disp16);
        break;
    case 0x27:
        /* STT */
        gen_store_fmem(ctx, &gen_stt, ra, rb, disp16);
        break;
    case 0x28:
        /* LDL */
        gen_load_mem(ctx, &gen_ldl, ra, rb, disp16, 0);
        break;
    case 0x29:
        /* LDQ */
        gen_load_mem(ctx, &gen_ldq, ra, rb, disp16, 0);
        break;
    case 0x2A:
        /* LDL_L */
        gen_load_mem(ctx, &gen_ldl_l, ra, rb, disp16, 0);
        break;
    case 0x2B:
        /* LDQ_L */
        gen_load_mem(ctx, &gen_ldq_l, ra, rb, disp16, 0);
        break;
    case 0x2C:
        /* STL */
        gen_store_mem(ctx, &gen_stl, ra, rb, disp16, 0);
        break;
    case 0x2D:
        /* STQ */
        gen_store_mem(ctx, &gen_stq, ra, rb, disp16, 0);
        break;
    case 0x2E:
        /* STL_C */
        gen_store_mem(ctx, &gen_stl_c, ra, rb, disp16, 0);
        break;
    case 0x2F:
        /* STQ_C */
        gen_store_mem(ctx, &gen_stq_c, ra, rb, disp16, 0);
        break;
    case 0x30:
        /* BR */
        gen_set_uT0(ctx, ctx->pc);
        gen_store_ir(ctx, ra, 0);
        if (disp21 != 0) {
            gen_set_sT1(ctx, disp21 << 2);
            gen_op_addq();
        }
        gen_op_branch();
        ret = 1;
        break;
    case 0x31:
        /* FBEQ */
        gen_fbcond(ctx, &gen_op_cmpfeq, ra, disp16);
        ret = 1;
        break;
    case 0x32:
        /* FBLT */
        gen_fbcond(ctx, &gen_op_cmpflt, ra, disp16);
        ret = 1;
        break;
    case 0x33:
        /* FBLE */
        gen_fbcond(ctx, &gen_op_cmpfle, ra, disp16);
        ret = 1;
        break;
    case 0x34:
        /* BSR */
        gen_set_uT0(ctx, ctx->pc);
        gen_store_ir(ctx, ra, 0);
        if (disp21 != 0) {
            gen_set_sT1(ctx, disp21 << 2);
            gen_op_addq();
        }
        gen_op_branch();
        ret = 1;
        break;
    case 0x35:
        /* FBNE */
        gen_fbcond(ctx, &gen_op_cmpfne, ra, disp16);
        ret = 1;
        break;
    case 0x36:
        /* FBGE */
        gen_fbcond(ctx, &gen_op_cmpfge, ra, disp16);
        ret = 1;
        break;
    case 0x37:
        /* FBGT */
        gen_fbcond(ctx, &gen_op_cmpfgt, ra, disp16);
        ret = 1;
        break;
    case 0x38:
        /* BLBC */
        gen_bcond(ctx, &gen_op_cmplbc, ra, disp16);
        ret = 1;
        break;
    case 0x39:
        /* BEQ */
        gen_bcond(ctx, &gen_op_cmpeqz, ra, disp16);
        ret = 1;
        break;
    case 0x3A:
        /* BLT */
        gen_bcond(ctx, &gen_op_cmpltz, ra, disp16);
        ret = 1;
        break;
    case 0x3B:
        /* BLE */
        gen_bcond(ctx, &gen_op_cmplez, ra, disp16);
        ret = 1;
        break;
    case 0x3C:
        /* BLBS */
        gen_bcond(ctx, &gen_op_cmplbs, ra, disp16);
        ret = 1;
        break;
    case 0x3D:
        /* BNE */
        gen_bcond(ctx, &gen_op_cmpnez, ra, disp16);
        ret = 1;
        break;
    case 0x3E:
        /* BGE */
        gen_bcond(ctx, &gen_op_cmpgez, ra, disp16);
        ret = 1;
        break;
    case 0x3F:
        /* BGT */
        gen_bcond(ctx, &gen_op_cmpgtz, ra, disp16);
        ret = 1;
        break;
    invalid_opc:
        gen_invalid(ctx);
        ret = 3;
        break;
    }

    return ret;
}

static always_inline int gen_intermediate_code_internal (CPUState *env,
                                                         TranslationBlock *tb,
                                                         int search_pc)
{
#if defined ALPHA_DEBUG_DISAS
    static int insn_count;
#endif
    DisasContext ctx, *ctxp = &ctx;
    target_ulong pc_start;
    uint32_t insn;
    uint16_t *gen_opc_end;
    int j, lj = -1;
    int ret;

    pc_start = tb->pc;
    gen_opc_ptr = gen_opc_buf;
    gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
    gen_opparam_ptr = gen_opparam_buf;
    nb_gen_labels = 0;
    ctx.pc = pc_start;
    ctx.amask = env->amask;
#if defined (CONFIG_USER_ONLY)
    ctx.mem_idx = 0;
#else
    ctx.mem_idx = ((env->ps >> 3) & 3);
    ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
#endif
    for (ret = 0; ret == 0;) {
        if (env->nb_breakpoints > 0) {
            for(j = 0; j < env->nb_breakpoints; j++) {
                if (env->breakpoints[j] == ctx.pc) {
                    gen_excp(&ctx, EXCP_DEBUG, 0);
                    break;
                }
            }
        }
        if (search_pc) {
            j = gen_opc_ptr - gen_opc_buf;
            if (lj < j) {
                lj++;
                while (lj < j)
                    gen_opc_instr_start[lj++] = 0;
                gen_opc_pc[lj] = ctx.pc;
                gen_opc_instr_start[lj] = 1;
            }
        }
#if defined ALPHA_DEBUG_DISAS
        insn_count++;
        if (logfile != NULL) {
            fprintf(logfile, "pc " TARGET_FMT_lx " mem_idx %d\n",
                    ctx.pc, ctx.mem_idx);
        }
#endif
        insn = ldl_code(ctx.pc);
#if defined ALPHA_DEBUG_DISAS
        insn_count++;
        if (logfile != NULL) {
            fprintf(logfile, "opcode %08x %d\n", insn, insn_count);
        }
#endif
        ctx.pc += 4;
        ret = translate_one(ctxp, insn);
        if (ret != 0)
            break;
        /* if we reach a page boundary or are single stepping, stop
         * generation
         */
        if (((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) ||
            (env->singlestep_enabled)) {
            break;
        }
#if defined (DO_SINGLE_STEP)
        break;
#endif
    }
    if (ret != 1 && ret != 3) {
        gen_update_pc(&ctx);
    }
    gen_op_reset_T0();
#if defined (DO_TB_FLUSH)
    gen_op_tb_flush();
#endif
    /* Generate the return instruction */
    gen_op_exit_tb();
    *gen_opc_ptr = INDEX_op_end;
    if (search_pc) {
        j = gen_opc_ptr - gen_opc_buf;
        lj++;
        while (lj <= j)
            gen_opc_instr_start[lj++] = 0;
    } else {
        tb->size = ctx.pc - pc_start;
    }
#if defined ALPHA_DEBUG_DISAS
    if (loglevel & CPU_LOG_TB_CPU) {
        cpu_dump_state(env, logfile, fprintf, 0);
    }
    if (loglevel & CPU_LOG_TB_IN_ASM) {
        fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
	target_disas(logfile, pc_start, ctx.pc - pc_start, 1);
        fprintf(logfile, "\n");
    }
    if (loglevel & CPU_LOG_TB_OP) {
        fprintf(logfile, "OP:\n");
        dump_ops(gen_opc_buf, gen_opparam_buf);
        fprintf(logfile, "\n");
    }
#endif

    return 0;
}

int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
{
    return gen_intermediate_code_internal(env, tb, 0);
}

int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
{
    return gen_intermediate_code_internal(env, tb, 1);
}

CPUAlphaState * cpu_alpha_init (const char *cpu_model)
{
    CPUAlphaState *env;
    uint64_t hwpcb;

    env = qemu_mallocz(sizeof(CPUAlphaState));
    if (!env)
        return NULL;
    cpu_exec_init(env);
    tlb_flush(env, 1);
    /* XXX: should not be hardcoded */
    env->implver = IMPLVER_2106x;
    env->ps = 0x1F00;
#if defined (CONFIG_USER_ONLY)
    env->ps |= 1 << 3;
#endif
    pal_init(env);
    /* Initialize IPR */
    hwpcb = env->ipr[IPR_PCBB];
    env->ipr[IPR_ASN] = 0;
    env->ipr[IPR_ASTEN] = 0;
    env->ipr[IPR_ASTSR] = 0;
    env->ipr[IPR_DATFX] = 0;
    /* XXX: fix this */
    //    env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
    //    env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
    //    env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
    //    env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
    env->ipr[IPR_FEN] = 0;
    env->ipr[IPR_IPL] = 31;
    env->ipr[IPR_MCES] = 0;
    env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
    //    env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
    env->ipr[IPR_SISR] = 0;
    env->ipr[IPR_VIRBND] = -1ULL;

    return env;
}