translate.c.svn-base

我们自己开发的一个OSEK操作系统！不知道可不可以？

    gen_store_fir(ctx, rc, 0);
}

static always_inline void gen_farith3 (DisasContext *ctx,
                                       void (*gen_arith_fop)(void),
                                       int ra, int rb, int rc)
{
    gen_load_fir(ctx, ra, 0);
    gen_load_fir(ctx, rb, 1);
    (*gen_arith_fop)();
    gen_store_fir(ctx, rc, 0);
}

static always_inline void gen_fcmov (DisasContext *ctx,
                                     void (*gen_test_fop)(void),
                                     int ra, int rb, int rc)
{
    gen_load_fir(ctx, ra, 0);
    gen_load_fir(ctx, rb, 1);
    (*gen_test_fop)();
    gen_op_cmov_fir(rc);
}

static always_inline void gen_fti (DisasContext *ctx,
                                   void (*gen_move_fop)(void),
                                   int ra, int rc)
{
    gen_load_fir(ctx, rc, 0);
    (*gen_move_fop)();
    gen_store_ir(ctx, ra, 0);
}

static always_inline void gen_itf (DisasContext *ctx,
                                   void (*gen_move_fop)(void),
                                   int ra, int rc)
{
    gen_load_ir(ctx, ra, 0);
    (*gen_move_fop)();
    gen_store_fir(ctx, rc, 0);
}

static always_inline void gen_s4addl (void)
{
    gen_op_s4();
    gen_op_addl();
}

static always_inline void gen_s4subl (void)
{
    gen_op_s4();
    gen_op_subl();
}

static always_inline void gen_s8addl (void)
{
    gen_op_s8();
    gen_op_addl();
}

static always_inline void gen_s8subl (void)
{
    gen_op_s8();
    gen_op_subl();
}

static always_inline void gen_s4addq (void)
{
    gen_op_s4();
    gen_op_addq();
}

static always_inline void gen_s4subq (void)
{
    gen_op_s4();
    gen_op_subq();
}

static always_inline void gen_s8addq (void)
{
    gen_op_s8();
    gen_op_addq();
}

static always_inline void gen_s8subq (void)
{
    gen_op_s8();
    gen_op_subq();
}

static always_inline void gen_amask (void)
{
    gen_op_load_amask();
    gen_op_bic();
}

static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
{
    uint32_t palcode;
    int32_t disp21, disp16, disp12;
    uint16_t fn11, fn16;
    uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit;
    int8_t lit;
    int ret;

    /* Decode all instruction fields */
    opc = insn >> 26;
    ra = (insn >> 21) & 0x1F;
    rb = (insn >> 16) & 0x1F;
    rc = insn & 0x1F;
    sbz = (insn >> 13) & 0x07;
    islit = (insn >> 12) & 1;
    lit = (insn >> 13) & 0xFF;
    palcode = insn & 0x03FFFFFF;
    disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11;
    disp16 = (int16_t)(insn & 0x0000FFFF);
    disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20;
    fn16 = insn & 0x0000FFFF;
    fn11 = (insn >> 5) & 0x000007FF;
    fpfn = fn11 & 0x3F;
    fn7 = (insn >> 5) & 0x0000007F;
    fn2 = (insn >> 5) & 0x00000003;
    ret = 0;
#if defined ALPHA_DEBUG_DISAS
    if (logfile != NULL) {
        fprintf(logfile, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
                opc, ra, rb, rc, disp16);
    }
#endif
    switch (opc) {
    case 0x00:
        /* CALL_PAL */
        if (palcode >= 0x80 && palcode < 0xC0) {
            /* Unprivileged PAL call */
            gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x1F) << 6), 0);
#if !defined (CONFIG_USER_ONLY)
        } else if (palcode < 0x40) {
            /* Privileged PAL code */
            if (ctx->mem_idx & 1)
                goto invalid_opc;
            else
                gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x1F) << 6), 0);
#endif
        } else {
            /* Invalid PAL call */
            goto invalid_opc;
        }
        ret = 3;
        break;
    case 0x01:
        /* OPC01 */
        goto invalid_opc;
    case 0x02:
        /* OPC02 */
        goto invalid_opc;
    case 0x03:
        /* OPC03 */
        goto invalid_opc;
    case 0x04:
        /* OPC04 */
        goto invalid_opc;
    case 0x05:
        /* OPC05 */
        goto invalid_opc;
    case 0x06:
        /* OPC06 */
        goto invalid_opc;
    case 0x07:
        /* OPC07 */
        goto invalid_opc;
    case 0x08:
        /* LDA */
        gen_load_ir(ctx, rb, 0);
        gen_set_sT1(ctx, disp16);
        gen_op_addq();
        gen_store_ir(ctx, ra, 0);
        break;
    case 0x09:
        /* LDAH */
        gen_load_ir(ctx, rb, 0);
        gen_set_sT1(ctx, disp16 << 16);
        gen_op_addq();
        gen_store_ir(ctx, ra, 0);
        break;
    case 0x0A:
        /* LDBU */
        if (!(ctx->amask & AMASK_BWX))
            goto invalid_opc;
        gen_load_mem(ctx, &gen_ldbu, ra, rb, disp16, 0);
        break;
    case 0x0B:
        /* LDQ_U */
        gen_load_mem(ctx, &gen_ldq_u, ra, rb, disp16, 1);
        break;
    case 0x0C:
        /* LDWU */
        if (!(ctx->amask & AMASK_BWX))
            goto invalid_opc;
        gen_load_mem(ctx, &gen_ldwu, ra, rb, disp16, 0);
        break;
    case 0x0D:
        /* STW */
        if (!(ctx->amask & AMASK_BWX))
            goto invalid_opc;
        gen_store_mem(ctx, &gen_stw, ra, rb, disp16, 0);
        break;
    case 0x0E:
        /* STB */
        if (!(ctx->amask & AMASK_BWX))
            goto invalid_opc;
        gen_store_mem(ctx, &gen_stb, ra, rb, disp16, 0);
        break;
    case 0x0F:
        /* STQ_U */
        gen_store_mem(ctx, &gen_stq_u, ra, rb, disp16, 1);
        break;
    case 0x10:
        switch (fn7) {
        case 0x00:
            /* ADDL */
            gen_arith3(ctx, &gen_op_addl, ra, rb, rc, islit, lit);
            break;
        case 0x02:
            /* S4ADDL */
            gen_arith3(ctx, &gen_s4addl, ra, rb, rc, islit, lit);
            break;
        case 0x09:
            /* SUBL */
            gen_arith3(ctx, &gen_op_subl, ra, rb, rc, islit, lit);
            break;
        case 0x0B:
            /* S4SUBL */
            gen_arith3(ctx, &gen_s4subl, ra, rb, rc, islit, lit);
            break;
        case 0x0F:
            /* CMPBGE */
            gen_arith3(ctx, &gen_op_cmpbge, ra, rb, rc, islit, lit);
            break;
        case 0x12:
            /* S8ADDL */
            gen_arith3(ctx, &gen_s8addl, ra, rb, rc, islit, lit);
            break;
        case 0x1B:
            /* S8SUBL */
            gen_arith3(ctx, &gen_s8subl, ra, rb, rc, islit, lit);
            break;
        case 0x1D:
            /* CMPULT */
            gen_arith3(ctx, &gen_op_cmpult, ra, rb, rc, islit, lit);
            break;
        case 0x20:
            /* ADDQ */
            gen_arith3(ctx, &gen_op_addq, ra, rb, rc, islit, lit);
            break;
        case 0x22:
            /* S4ADDQ */
            gen_arith3(ctx, &gen_s4addq, ra, rb, rc, islit, lit);
            break;
        case 0x29:
            /* SUBQ */
            gen_arith3(ctx, &gen_op_subq, ra, rb, rc, islit, lit);
            break;
        case 0x2B:
            /* S4SUBQ */
            gen_arith3(ctx, &gen_s4subq, ra, rb, rc, islit, lit);
            break;
        case 0x2D:
            /* CMPEQ */
            gen_arith3(ctx, &gen_op_cmpeq, ra, rb, rc, islit, lit);
            break;
        case 0x32:
            /* S8ADDQ */
            gen_arith3(ctx, &gen_s8addq, ra, rb, rc, islit, lit);
            break;
        case 0x3B:
            /* S8SUBQ */
            gen_arith3(ctx, &gen_s8subq, ra, rb, rc, islit, lit);
            break;
        case 0x3D:
            /* CMPULE */
            gen_arith3(ctx, &gen_op_cmpule, ra, rb, rc, islit, lit);
            break;
        case 0x40:
            /* ADDL/V */
            gen_arith3(ctx, &gen_op_addlv, ra, rb, rc, islit, lit);
            break;
        case 0x49:
            /* SUBL/V */
            gen_arith3(ctx, &gen_op_sublv, ra, rb, rc, islit, lit);
            break;
        case 0x4D:
            /* CMPLT */
            gen_arith3(ctx, &gen_op_cmplt, ra, rb, rc, islit, lit);
            break;
        case 0x60:
            /* ADDQ/V */
            gen_arith3(ctx, &gen_op_addqv, ra, rb, rc, islit, lit);
            break;
        case 0x69:
            /* SUBQ/V */
            gen_arith3(ctx, &gen_op_subqv, ra, rb, rc, islit, lit);
            break;
        case 0x6D:
            /* CMPLE */
            gen_arith3(ctx, &gen_op_cmple, ra, rb, rc, islit, lit);
            break;
        default:
            goto invalid_opc;
        }
        break;
    case 0x11:
        switch (fn7) {
        case 0x00:
            /* AND */
            gen_arith3(ctx, &gen_op_and, ra, rb, rc, islit, lit);
            break;
        case 0x08:
            /* BIC */
            gen_arith3(ctx, &gen_op_bic, ra, rb, rc, islit, lit);
            break;
        case 0x14:
            /* CMOVLBS */
            gen_cmov(ctx, &gen_op_cmplbs, ra, rb, rc, islit, lit);
            break;
        case 0x16:
            /* CMOVLBC */
            gen_cmov(ctx, &gen_op_cmplbc, ra, rb, rc, islit, lit);
            break;
        case 0x20:
            /* BIS */
            if (ra == rb || ra == 31 || rb == 31) {
                if (ra == 31 && rc == 31) {
                    /* NOP */
                    gen_op_nop();
                } else {
                    /* MOV */
                    gen_load_ir(ctx, rb, 0);
                    gen_store_ir(ctx, rc, 0);
                }
            } else {
                gen_arith3(ctx, &gen_op_bis, ra, rb, rc, islit, lit);
            }
            break;
        case 0x24:
            /* CMOVEQ */
            gen_cmov(ctx, &gen_op_cmpeqz, ra, rb, rc, islit, lit);
            break;
        case 0x26:
            /* CMOVNE */
            gen_cmov(ctx, &gen_op_cmpnez, ra, rb, rc, islit, lit);
            break;
        case 0x28:
            /* ORNOT */
            gen_arith3(ctx, &gen_op_ornot, ra, rb, rc, islit, lit);
            break;
        case 0x40:
            /* XOR */
            gen_arith3(ctx, &gen_op_xor, ra, rb, rc, islit, lit);
            break;
        case 0x44:
            /* CMOVLT */
            gen_cmov(ctx, &gen_op_cmpltz, ra, rb, rc, islit, lit);
            break;
        case 0x46:
            /* CMOVGE */
            gen_cmov(ctx, &gen_op_cmpgez, ra, rb, rc, islit, lit);
            break;
        case 0x48:
            /* EQV */
            gen_arith3(ctx, &gen_op_eqv, ra, rb, rc, islit, lit);
            break;
        case 0x61:
            /* AMASK */
            gen_arith2(ctx, &gen_amask, rb, rc, islit, lit);
            break;
        case 0x64:
            /* CMOVLE */
            gen_cmov(ctx, &gen_op_cmplez, ra, rb, rc, islit, lit);
            break;
        case 0x66:
            /* CMOVGT */
            gen_cmov(ctx, &gen_op_cmpgtz, ra, rb, rc, islit, lit);
            break;
        case 0x6C:
            /* IMPLVER */
            gen_op_load_implver();
            gen_store_ir(ctx, rc, 0);
            break;
        default:
            goto invalid_opc;
        }
        break;
    case 0x12:
        switch (fn7) {
        case 0x02:
            /* MSKBL */
            gen_arith3(ctx, &gen_op_mskbl, ra, rb, rc, islit, lit);
            break;
        case 0x06:
            /* EXTBL */
            gen_arith3(ctx, &gen_op_extbl, ra, rb, rc, islit, lit);
            break;
        case 0x0B:
            /* INSBL */
            gen_arith3(ctx, &gen_op_insbl, ra, rb, rc, islit, lit);
            break;
        case 0x12:
            /* MSKWL */
            gen_arith3(ctx, &gen_op_mskwl, ra, rb, rc, islit, lit);
            break;
        case 0x16:
            /* EXTWL */
            gen_arith3(ctx, &gen_op_extwl, ra, rb, rc, islit, lit);
            break;
        case 0x1B:
            /* INSWL */
            gen_arith3(ctx, &gen_op_inswl, ra, rb, rc, islit, lit);
            break;
        case 0x22:
            /* MSKLL */
            gen_arith3(ctx, &gen_op_mskll, ra, rb, rc, islit, lit);
            break;
        case 0x26:
            /* EXTLL */
            gen_arith3(ctx, &gen_op_extll, ra, rb, rc, islit, lit);
            break;
        case 0x2B:
            /* INSLL */
            gen_arith3(ctx, &gen_op_insll, ra, rb, rc, islit, lit);
            break;
        case 0x30:
            /* ZAP */
            gen_arith3(ctx, &gen_op_zap, ra, rb, rc, islit, lit);
            break;
        case 0x31:
            /* ZAPNOT */
            gen_arith3(ctx, &gen_op_zapnot, ra, rb, rc, islit, lit);
            break;
        case 0x32:
            /* MSKQL */
            gen_arith3(ctx, &gen_op_mskql, ra, rb, rc, islit, lit);
            break;
        case 0x34:
            /* SRL */
            gen_arith3(ctx, &gen_op_srl, ra, rb, rc, islit, lit);
            break;
        case 0x36:
            /* EXTQL */
            gen_arith3(ctx, &gen_op_extql, ra, rb, rc, islit, lit);
            break;
        case 0x39:
            /* SLL */
            gen_arith3(ctx, &gen_op_sll, ra, rb, rc, islit, lit);
            break;
        case 0x3B:
            /* INSQL */
            gen_arith3(ctx, &gen_op_insql, ra, rb, rc, islit, lit);
            break;
        case 0x3C:
            /* SRA */
            gen_arith3(ctx, &gen_op_sra, ra, rb, rc, islit, lit);
            break;
        case 0x52:
            /* MSKWH */
            gen_arith3(ctx, &gen_op_mskwh, ra, rb, rc, islit, lit);
            break;
        case 0x57:
            /* INSWH */
            gen_arith3(ctx, &gen_op_inswh, ra, rb, rc, islit, lit);
            break;
        case 0x5A:
            /* EXTWH */
            gen_arith3(ctx, &gen_op_extwh, ra, rb, rc, islit, lit);
            break;
        case 0x62:
            /* MSKLH */
            gen_arith3(ctx, &gen_op_msklh, ra, rb, rc, islit, lit);
            break;
        case 0x67:
            /* INSLH */
            gen_arith3(ctx, &gen_op_inslh, ra, rb, rc, islit, lit);
            break;
        case 0x6A:
            /* EXTLH */
            gen_arith3(ctx, &gen_op_extlh, ra, rb, rc, islit, lit);
            break;
        case 0x72:
            /* MSKQH */
            gen_arith3(ctx, &gen_op_mskqh, ra, rb, rc, islit, lit);
            break;
        case 0x77:
            /* INSQH */
            gen_arith3(ctx, &gen_op_insqh, ra, rb, rc, islit, lit);
            break;
        case 0x7A:
            /* EXTQH */
            gen_arith3(ctx, &gen_op_extqh, ra, rb, rc, islit, lit);
            break;
        default:
            goto invalid_opc;
        }
        break;
    case 0x13:
        switch (fn7) {
        case 0x00:
            /* MULL */
            gen_arith3(ctx, &gen_op_mull, ra, rb, rc, islit, lit);
            break;
        case 0x20:
            /* MULQ */
            gen_arith3(ctx, &gen_op_mulq, ra, rb, rc, islit, lit);
            break;
        case 0x30:
            /* UMULH */
            gen_arith3(ctx, &gen_op_umulh, ra, rb, rc, islit, lit);
            break;
        case 0x40:
            /* MULL/V */
            gen_arith3(ctx, &gen_op_mullv, ra, rb, rc, islit, lit);
            break;
        case 0x60:
            /* MULQ/V */
            gen_arith3(ctx, &gen_op_mulqv, ra, rb, rc, islit, lit);
            break;
        default:
            goto invalid_opc;
        }
        break;
    case 0x14:
        switch (fpfn) { /* f11 & 0x3F */
        case 0x04:
            /* ITOFS */
            if (!(ctx->amask & AMASK_FIX))
                goto invalid_opc;
            gen_itf(ctx, &gen_op_itofs, ra, rc);
            break;