gdbstub.c.svn-base

我们自己开发的一个OSEK操作系统！不知道可不可以？

        uint64_t tmp = tswapl(registers[66]);

        PUT_CCR(env, tmp >> 32);
        env->asi = (tmp >> 24) & 0xff;
        env->pstate = (tmp >> 8) & 0xfff;
        PUT_CWP64(env, tmp & 0xff);
    }
    env->fsr = tswapl(registers[67]);
    env->fprs = tswapl(registers[68]);
    env->y = tswapl(registers[69]);
#endif
}
#elif defined (TARGET_ARM)
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
{
    int i;
    uint8_t *ptr;

    ptr = mem_buf;
    /* 16 core integer registers (4 bytes each).  */
    for (i = 0; i < 16; i++)
      {
        *(uint32_t *)ptr = tswapl(env->regs[i]);
        ptr += 4;
      }
    /* 8 FPA registers (12 bytes each), FPS (4 bytes).
       Not yet implemented.  */
    memset (ptr, 0, 8 * 12 + 4);
    ptr += 8 * 12 + 4;
    /* CPSR (4 bytes).  */
    *(uint32_t *)ptr = tswapl (cpsr_read(env));
    ptr += 4;

    return ptr - mem_buf;
}

static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
{
    int i;
    uint8_t *ptr;

    ptr = mem_buf;
    /* Core integer registers.  */
    for (i = 0; i < 16; i++)
      {
        env->regs[i] = tswapl(*(uint32_t *)ptr);
        ptr += 4;
      }
    /* Ignore FPA regs and scr.  */
    ptr += 8 * 12 + 4;
    cpsr_write (env, tswapl(*(uint32_t *)ptr), 0xffffffff);
}
#elif defined (TARGET_M68K)
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
{
    int i;
    uint8_t *ptr;
    CPU_DoubleU u;

    ptr = mem_buf;
    /* D0-D7 */
    for (i = 0; i < 8; i++) {
        *(uint32_t *)ptr = tswapl(env->dregs[i]);
        ptr += 4;
    }
    /* A0-A7 */
    for (i = 0; i < 8; i++) {
        *(uint32_t *)ptr = tswapl(env->aregs[i]);
        ptr += 4;
    }
    *(uint32_t *)ptr = tswapl(env->sr);
    ptr += 4;
    *(uint32_t *)ptr = tswapl(env->pc);
    ptr += 4;
    /* F0-F7.  The 68881/68040 have 12-bit extended precision registers.
       ColdFire has 8-bit double precision registers.  */
    for (i = 0; i < 8; i++) {
        u.d = env->fregs[i];
        *(uint32_t *)ptr = tswap32(u.l.upper);
        *(uint32_t *)ptr = tswap32(u.l.lower);
    }
    /* FP control regs (not implemented).  */
    memset (ptr, 0, 3 * 4);
    ptr += 3 * 4;

    return ptr - mem_buf;
}

static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
{
    int i;
    uint8_t *ptr;
    CPU_DoubleU u;

    ptr = mem_buf;
    /* D0-D7 */
    for (i = 0; i < 8; i++) {
        env->dregs[i] = tswapl(*(uint32_t *)ptr);
        ptr += 4;
    }
    /* A0-A7 */
    for (i = 0; i < 8; i++) {
        env->aregs[i] = tswapl(*(uint32_t *)ptr);
        ptr += 4;
    }
    env->sr = tswapl(*(uint32_t *)ptr);
    ptr += 4;
    env->pc = tswapl(*(uint32_t *)ptr);
    ptr += 4;
    /* F0-F7.  The 68881/68040 have 12-bit extended precision registers.
       ColdFire has 8-bit double precision registers.  */
    for (i = 0; i < 8; i++) {
        u.l.upper = tswap32(*(uint32_t *)ptr);
        u.l.lower = tswap32(*(uint32_t *)ptr);
        env->fregs[i] = u.d;
    }
    /* FP control regs (not implemented).  */
    ptr += 3 * 4;
}
#elif defined (TARGET_MIPS)
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
{
    int i;
    uint8_t *ptr;

    ptr = mem_buf;
    for (i = 0; i < 32; i++)
      {
        *(target_ulong *)ptr = tswapl(env->gpr[i][env->current_tc]);
        ptr += sizeof(target_ulong);
      }

    *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Status);
    ptr += sizeof(target_ulong);

    *(target_ulong *)ptr = tswapl(env->LO[0][env->current_tc]);
    ptr += sizeof(target_ulong);

    *(target_ulong *)ptr = tswapl(env->HI[0][env->current_tc]);
    ptr += sizeof(target_ulong);

    *(target_ulong *)ptr = tswapl(env->CP0_BadVAddr);
    ptr += sizeof(target_ulong);

    *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Cause);
    ptr += sizeof(target_ulong);

    *(target_ulong *)ptr = tswapl(env->PC[env->current_tc]);
    ptr += sizeof(target_ulong);

    if (env->CP0_Config1 & (1 << CP0C1_FP))
      {
        for (i = 0; i < 32; i++)
          {
            if (env->CP0_Status & (1 << CP0St_FR))
              *(target_ulong *)ptr = tswapl(env->fpu->fpr[i].d);
            else
              *(target_ulong *)ptr = tswap32(env->fpu->fpr[i].w[FP_ENDIAN_IDX]);
            ptr += sizeof(target_ulong);
          }

        *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr31);
        ptr += sizeof(target_ulong);

        *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr0);
        ptr += sizeof(target_ulong);
      }

    /* "fp", pseudo frame pointer. Not yet implemented in gdb. */
    *(target_ulong *)ptr = 0;
    ptr += sizeof(target_ulong);

    /* Registers for embedded use, we just pad them. */
    for (i = 0; i < 16; i++)
      {
        *(target_ulong *)ptr = 0;
        ptr += sizeof(target_ulong);
      }

    /* Processor ID. */
    *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_PRid);
    ptr += sizeof(target_ulong);

    return ptr - mem_buf;
}

/* convert MIPS rounding mode in FCR31 to IEEE library */
static unsigned int ieee_rm[] =
  {
    float_round_nearest_even,
    float_round_to_zero,
    float_round_up,
    float_round_down
  };
#define RESTORE_ROUNDING_MODE \
    set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)

static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
{
    int i;
    uint8_t *ptr;

    ptr = mem_buf;
    for (i = 0; i < 32; i++)
      {
        env->gpr[i][env->current_tc] = tswapl(*(target_ulong *)ptr);
        ptr += sizeof(target_ulong);
      }

    env->CP0_Status = tswapl(*(target_ulong *)ptr);
    ptr += sizeof(target_ulong);

    env->LO[0][env->current_tc] = tswapl(*(target_ulong *)ptr);
    ptr += sizeof(target_ulong);

    env->HI[0][env->current_tc] = tswapl(*(target_ulong *)ptr);
    ptr += sizeof(target_ulong);

    env->CP0_BadVAddr = tswapl(*(target_ulong *)ptr);
    ptr += sizeof(target_ulong);

    env->CP0_Cause = tswapl(*(target_ulong *)ptr);
    ptr += sizeof(target_ulong);

    env->PC[env->current_tc] = tswapl(*(target_ulong *)ptr);
    ptr += sizeof(target_ulong);

    if (env->CP0_Config1 & (1 << CP0C1_FP))
      {
        for (i = 0; i < 32; i++)
          {
            if (env->CP0_Status & (1 << CP0St_FR))
              env->fpu->fpr[i].d = tswapl(*(target_ulong *)ptr);
            else
              env->fpu->fpr[i].w[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr);
            ptr += sizeof(target_ulong);
          }

        env->fpu->fcr31 = tswapl(*(target_ulong *)ptr) & 0xFF83FFFF;
        ptr += sizeof(target_ulong);

        /* The remaining registers are assumed to be read-only. */

        /* set rounding mode */
        RESTORE_ROUNDING_MODE;

#ifndef CONFIG_SOFTFLOAT
        /* no floating point exception for native float */
        SET_FP_ENABLE(env->fcr31, 0);
#endif
      }
}
#elif defined (TARGET_SH4)

/* Hint: Use "set architecture sh4" in GDB to see fpu registers */

static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
{
  uint32_t *ptr = (uint32_t *)mem_buf;
  int i;

#define SAVE(x) *ptr++=tswapl(x)
  if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
      for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
  } else {
      for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
  }
  for (i = 8; i < 16; i++) SAVE(env->gregs[i]);
  SAVE (env->pc);
  SAVE (env->pr);
  SAVE (env->gbr);
  SAVE (env->vbr);
  SAVE (env->mach);
  SAVE (env->macl);
  SAVE (env->sr);
  SAVE (env->fpul);
  SAVE (env->fpscr);
  for (i = 0; i < 16; i++)
      SAVE(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
  SAVE (env->ssr);
  SAVE (env->spc);
  for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
  for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
  return ((uint8_t *)ptr - mem_buf);
}

static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
{
  uint32_t *ptr = (uint32_t *)mem_buf;
  int i;

#define LOAD(x) (x)=*ptr++;
  if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
      for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
  } else {
      for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
  }
  for (i = 8; i < 16; i++) LOAD(env->gregs[i]);
  LOAD (env->pc);
  LOAD (env->pr);
  LOAD (env->gbr);
  LOAD (env->vbr);
  LOAD (env->mach);
  LOAD (env->macl);
  LOAD (env->sr);
  LOAD (env->fpul);
  LOAD (env->fpscr);
  for (i = 0; i < 16; i++)
      LOAD(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
  LOAD (env->ssr);
  LOAD (env->spc);
  for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
  for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
}
#elif defined (TARGET_CRIS)

static int cris_save_32 (unsigned char *d, uint32_t value)
{
	*d++ = (value);
	*d++ = (value >>= 8);
	*d++ = (value >>= 8);
	*d++ = (value >>= 8);
	return 4;
}
static int cris_save_16 (unsigned char *d, uint32_t value)
{
	*d++ = (value);
	*d++ = (value >>= 8);
	return 2;
}
static int cris_save_8 (unsigned char *d, uint32_t value)
{
	*d++ = (value);
	return 1;
}

/* FIXME: this will bug on archs not supporting unaligned word accesses.  */
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
{
  uint8_t *ptr = mem_buf;
  uint8_t srs;
  int i;

  for (i = 0; i < 16; i++)
	  ptr += cris_save_32 (ptr, env->regs[i]);

  srs = env->pregs[SR_SRS];

  ptr += cris_save_8 (ptr, env->pregs[0]);
  ptr += cris_save_8 (ptr, env->pregs[1]);
  ptr += cris_save_32 (ptr, env->pregs[2]);
  ptr += cris_save_8 (ptr, srs);
  ptr += cris_save_16 (ptr, env->pregs[4]);

  for (i = 5; i < 16; i++)
	  ptr += cris_save_32 (ptr, env->pregs[i]);

  ptr += cris_save_32 (ptr, env->pc);

  for (i = 0; i < 16; i++)
	  ptr += cris_save_32 (ptr, env->sregs[srs][i]);

  return ((uint8_t *)ptr - mem_buf);
}

static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
{
  uint32_t *ptr = (uint32_t *)mem_buf;
  int i;

#define LOAD(x) (x)=*ptr++;
  for (i = 0; i < 16; i++) LOAD(env->regs[i]);
  LOAD (env->pc);
}
#else
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
{
    return 0;
}

static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
{
}

#endif

static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
{
    const char *p;
    int ch, reg_size, type;
    char buf[4096];
    uint8_t mem_buf[4096];
    uint32_t *registers;
    target_ulong addr, len;

#ifdef DEBUG_GDB
    printf("command='%s'\n", line_buf);
#endif
    p = line_buf;
    ch = *p++;
    switch(ch) {
    case '?':
        /* TODO: Make this return the correct value for user-mode.  */
        snprintf(buf, sizeof(buf), "S%02x", SIGTRAP);
        put_packet(s, buf);
        break;
    case 'c':
        if (*p != '\0') {
            addr = strtoull(p, (char **)&p, 16);
#if defined(TARGET_I386)
            env->eip = addr;
#elif defined (TARGET_PPC)
            env->nip = addr;
#elif defined (TARGET_SPARC)
            env->pc = addr;
            env->npc = addr + 4;
#elif defined (TARGET_ARM)
            env->regs[15] = addr;
#elif defined (TARGET_SH4)
            env->pc = addr;
#elif defined (TARGET_MIPS)
            env->PC[env->current_tc] = addr;
#elif defined (TARGET_CRIS)
            env->pc = addr;
#endif
        }
#ifdef CONFIG_USER_ONLY
        s->running_state = 1;
#else
        vm_start();
#endif
	return RS_IDLE;
    case 's':
        if (*p != '\0') {
            addr = strtoull(p, (char **)&p, 16);
#if defined(TARGET_I386)
            env->eip = addr;
#elif defined (TARGET_PPC)
            env->nip = addr;
#elif defined (TARGET_SPARC)
            env->pc = addr;
            env->npc = addr + 4;
#elif defined (TARGET_ARM)
            env->regs[15] = addr;
#elif defined (TARGET_SH4)
            env->pc = addr;
#elif defined (TARGET_MIPS)
            env->PC[env->current_tc] = addr;
#elif defined (TARGET_CRIS)
            env->pc = addr;
#endif
        }
        cpu_single_step(env, 1);
#ifdef CONFIG_USER_ONLY
        s->running_state = 1;
#else
        vm_start();
#endif
	return RS_IDLE;
    case 'F':
        {
            target_ulong ret;
            target_ulong err;

            ret = strtoull(p, (char **)&p, 16);
            if (*p == ',') {
                p++;
                err = strtoull(p, (char **)&p, 16);
            } else {
                err = 0;
            }
            if (*p == ',')
                p++;
            type = *p;
            if (gdb_current_syscall_cb)
                gdb_current_syscall_cb(s->env, ret, err);
            if (type == 'C') {
                put_packet(s, "T02");
            } else {
#ifdef CONFIG_USER_ONLY
                s->running_state = 1;
#else
                vm_start();
#endif