📄 alpha-dis.c.svn-base
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#define FP_(oo,fff) (OP(oo) | (((fff) & 0x7FF) << 5))#define FP_MASK (OP_MASK | 0xFFE0)#define FP(oo,fff) FP_(oo,fff), FP_MASK/* Memory format instructions */#define MEM_(oo) OP(oo)#define MEM_MASK OP_MASK#define MEM(oo) MEM_(oo), MEM_MASK/* Memory/Func Code format instructions */#define MFC_(oo,ffff) (OP(oo) | ((ffff) & 0xFFFF))#define MFC_MASK (OP_MASK | 0xFFFF)#define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK/* Memory/Branch format instructions */#define MBR_(oo,h) (OP(oo) | (((h) & 3) << 14))#define MBR_MASK (OP_MASK | 0xC000)#define MBR(oo,h) MBR_(oo,h), MBR_MASK/* Operate format instructions. The OPRL variant specifies a literal second argument. */#define OPR_(oo,ff) (OP(oo) | (((ff) & 0x7F) << 5))#define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000)#define OPR_MASK (OP_MASK | 0x1FE0)#define OPR(oo,ff) OPR_(oo,ff), OPR_MASK#define OPRL(oo,ff) OPRL_(oo,ff), OPR_MASK/* Generic PALcode format instructions */#define PCD_(oo) OP(oo)#define PCD_MASK OP_MASK#define PCD(oo) PCD_(oo), PCD_MASK/* Specific PALcode instructions */#define SPCD_(oo,ffff) (OP(oo) | ((ffff) & 0x3FFFFFF))#define SPCD_MASK 0xFFFFFFFF#define SPCD(oo,ffff) SPCD_(oo,ffff), SPCD_MASK/* Hardware memory (hw_{ld,st}) instructions */#define EV4HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))#define EV4HWMEM_MASK (OP_MASK | 0xF000)#define EV4HWMEM(oo,f) EV4HWMEM_(oo,f), EV4HWMEM_MASK#define EV5HWMEM_(oo,f) (OP(oo) | (((f) & 0x3F) << 10))#define EV5HWMEM_MASK (OP_MASK | 0xF800)#define EV5HWMEM(oo,f) EV5HWMEM_(oo,f), EV5HWMEM_MASK#define EV6HWMEM_(oo,f) (OP(oo) | (((f) & 0xF) << 12))#define EV6HWMEM_MASK (OP_MASK | 0xF000)#define EV6HWMEM(oo,f) EV6HWMEM_(oo,f), EV6HWMEM_MASK#define EV6HWMBR_(oo,h) (OP(oo) | (((h) & 7) << 13))#define EV6HWMBR_MASK (OP_MASK | 0xE000)#define EV6HWMBR(oo,h) EV6HWMBR_(oo,h), EV6HWMBR_MASK/* Abbreviations for instruction subsets. */#define BASE AXP_OPCODE_BASE#define EV4 AXP_OPCODE_EV4#define EV5 AXP_OPCODE_EV5#define EV6 AXP_OPCODE_EV6#define BWX AXP_OPCODE_BWX#define CIX AXP_OPCODE_CIX#define MAX AXP_OPCODE_MAX/* Common combinations of arguments */#define ARG_NONE { 0 }#define ARG_BRA { RA, BDISP }#define ARG_FBRA { FA, BDISP }#define ARG_FP { FA, FB, DFC1 }#define ARG_FPZ1 { ZA, FB, DFC1 }#define ARG_MEM { RA, MDISP, PRB }#define ARG_FMEM { FA, MDISP, PRB }#define ARG_OPR { RA, RB, DRC1 }#define ARG_OPRL { RA, LIT, DRC1 }#define ARG_OPRZ1 { ZA, RB, DRC1 }#define ARG_OPRLZ1 { ZA, LIT, RC }#define ARG_PCD { PALFN }#define ARG_EV4HWMEM { RA, EV4HWDISP, PRB }#define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX }#define ARG_EV5HWMEM { RA, EV5HWDISP, PRB }#define ARG_EV6HWMEM { RA, EV6HWDISP, PRB } /* The opcode table. The format of the opcode table is: NAME OPCODE MASK { OPERANDS } NAME is the name of the instruction. OPCODE is the instruction opcode. MASK is the opcode mask; this is used to tell the disassembler which bits in the actual opcode must match OPCODE. OPERANDS is the list of operands. The preceding macros merge the text of the OPCODE and MASK fields. The disassembler reads the table in order and prints the first instruction which matches, so this table is sorted to put more specific instructions before more general instructions. Otherwise, it is sorted by major opcode and minor function code. There are three classes of not-really-instructions in this table: ALIAS is another name for another instruction. Some of these come from the Architecture Handbook, some come from the original gas opcode tables. In all cases, the functionality of the opcode is unchanged. PSEUDO a stylized code form endorsed by Chapter A.4 of the Architecture Handbook. EXTRA a stylized code form found in the original gas tables. And two annotations: EV56 BUT opcodes that are officially introduced as of the ev56, but with defined results on previous implementations. EV56 UNA opcodes that were introduced as of the ev56 with presumably undefined results on previous implementations that were not assigned to a particular extension.*/const struct alpha_opcode alpha_opcodes[] = { { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE }, { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE }, { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE }, { "bugchk", SPCD(0x00,0x0081), BASE, ARG_NONE }, { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE }, { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE }, { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE }, { "rduniq", SPCD(0x00,0x009e), BASE, ARG_NONE }, { "wruniq", SPCD(0x00,0x009f), BASE, ARG_NONE }, { "gentrap", SPCD(0x00,0x00aa), BASE, ARG_NONE }, { "call_pal", PCD(0x00), BASE, ARG_PCD }, { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */ { "lda", MEM(0x08), BASE, { RA, MDISP, ZB } }, /* pseudo */ { "lda", MEM(0x08), BASE, ARG_MEM }, { "ldah", MEM(0x09), BASE, { RA, MDISP, ZB } }, /* pseudo */ { "ldah", MEM(0x09), BASE, ARG_MEM }, { "ldbu", MEM(0x0A), BWX, ARG_MEM }, { "unop", MEM_(0x0B) | (30 << 16), MEM_MASK, BASE, { ZA } }, /* pseudo */ { "ldq_u", MEM(0x0B), BASE, ARG_MEM }, { "ldwu", MEM(0x0C), BWX, ARG_MEM }, { "stw", MEM(0x0D), BWX, ARG_MEM }, { "stb", MEM(0x0E), BWX, ARG_MEM }, { "stq_u", MEM(0x0F), BASE, ARG_MEM }, { "sextl", OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */ { "sextl", OPRL(0x10,0x00), BASE, ARG_OPRLZ1 }, /* pseudo */ { "addl", OPR(0x10,0x00), BASE, ARG_OPR }, { "addl", OPRL(0x10,0x00), BASE, ARG_OPRL }, { "s4addl", OPR(0x10,0x02), BASE, ARG_OPR }, { "s4addl", OPRL(0x10,0x02), BASE, ARG_OPRL }, { "negl", OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */ { "negl", OPRL(0x10,0x09), BASE, ARG_OPRLZ1 }, /* pseudo */ { "subl", OPR(0x10,0x09), BASE, ARG_OPR }, { "subl", OPRL(0x10,0x09), BASE, ARG_OPRL }, { "s4subl", OPR(0x10,0x0B), BASE, ARG_OPR }, { "s4subl", OPRL(0x10,0x0B), BASE, ARG_OPRL }, { "cmpbge", OPR(0x10,0x0F), BASE, ARG_OPR }, { "cmpbge", OPRL(0x10,0x0F), BASE, ARG_OPRL }, { "s8addl", OPR(0x10,0x12), BASE, ARG_OPR }, { "s8addl", OPRL(0x10,0x12), BASE, ARG_OPRL }, { "s8subl", OPR(0x10,0x1B), BASE, ARG_OPR }, { "s8subl", OPRL(0x10,0x1B), BASE, ARG_OPRL }, { "cmpult", OPR(0x10,0x1D), BASE, ARG_OPR }, { "cmpult", OPRL(0x10,0x1D), BASE, ARG_OPRL }, { "addq", OPR(0x10,0x20), BASE, ARG_OPR }, { "addq", OPRL(0x10,0x20), BASE, ARG_OPRL }, { "s4addq", OPR(0x10,0x22), BASE, ARG_OPR }, { "s4addq", OPRL(0x10,0x22), BASE, ARG_OPRL }, { "negq", OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */ { "negq", OPRL(0x10,0x29), BASE, ARG_OPRLZ1 }, /* pseudo */ { "subq", OPR(0x10,0x29), BASE, ARG_OPR }, { "subq", OPRL(0x10,0x29), BASE, ARG_OPRL }, { "s4subq", OPR(0x10,0x2B), BASE, ARG_OPR }, { "s4subq", OPRL(0x10,0x2B), BASE, ARG_OPRL }, { "cmpeq", OPR(0x10,0x2D), BASE, ARG_OPR }, { "cmpeq", OPRL(0x10,0x2D), BASE, ARG_OPRL }, { "s8addq", OPR(0x10,0x32), BASE, ARG_OPR }, { "s8addq", OPRL(0x10,0x32), BASE, ARG_OPRL }, { "s8subq", OPR(0x10,0x3B), BASE, ARG_OPR }, { "s8subq", OPRL(0x10,0x3B), BASE, ARG_OPRL }, { "cmpule", OPR(0x10,0x3D), BASE, ARG_OPR }, { "cmpule", OPRL(0x10,0x3D), BASE, ARG_OPRL }, { "addl/v", OPR(0x10,0x40), BASE, ARG_OPR }, { "addl/v", OPRL(0x10,0x40), BASE, ARG_OPRL }, { "negl/v", OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */ { "negl/v", OPRL(0x10,0x49), BASE, ARG_OPRLZ1 }, /* pseudo */ { "subl/v", OPR(0x10,0x49), BASE, ARG_OPR }, { "subl/v", OPRL(0x10,0x49), BASE, ARG_OPRL }, { "cmplt", OPR(0x10,0x4D), BASE, ARG_OPR }, { "cmplt", OPRL(0x10,0x4D), BASE, ARG_OPRL }, { "addq/v", OPR(0x10,0x60), BASE, ARG_OPR }, { "addq/v", OPRL(0x10,0x60), BASE, ARG_OPRL }, { "negq/v", OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */ { "negq/v", OPRL(0x10,0x69), BASE, ARG_OPRLZ1 }, /* pseudo */ { "subq/v", OPR(0x10,0x69), BASE, ARG_OPR }, { "subq/v", OPRL(0x10,0x69), BASE, ARG_OPRL }, { "cmple", OPR(0x10,0x6D), BASE, ARG_OPR }, { "cmple", OPRL(0x10,0x6D), BASE, ARG_OPRL }, { "and", OPR(0x11,0x00), BASE, ARG_OPR }, { "and", OPRL(0x11,0x00), BASE, ARG_OPRL }, { "andnot", OPR(0x11,0x08), BASE, ARG_OPR }, /* alias */ { "andnot", OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */ { "bic", OPR(0x11,0x08), BASE, ARG_OPR }, { "bic", OPRL(0x11,0x08), BASE, ARG_OPRL }, { "cmovlbs", OPR(0x11,0x14), BASE, ARG_OPR }, { "cmovlbs", OPRL(0x11,0x14), BASE, ARG_OPRL }, { "cmovlbc", OPR(0x11,0x16), BASE, ARG_OPR }, { "cmovlbc", OPRL(0x11,0x16), BASE, ARG_OPRL }, { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */ { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */ { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */ { "mov", OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */ { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */ { "or", OPR(0x11,0x20), BASE, ARG_OPR }, /* alias */ { "or", OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */ { "bis", OPR(0x11,0x20), BASE, ARG_OPR }, { "bis", OPRL(0x11,0x20), BASE, ARG_OPRL }, { "cmoveq", OPR(0x11,0x24), BASE, ARG_OPR }, { "cmoveq", OPRL(0x11,0x24), BASE, ARG_OPRL }, { "cmovne", OPR(0x11,0x26), BASE, ARG_OPR }, { "cmovne", OPRL(0x11,0x26), BASE, ARG_OPRL }, { "not", OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */ { "not", OPRL(0x11,0x28), BASE, ARG_OPRLZ1 }, /* pseudo */ { "ornot", OPR(0x11,0x28), BASE, ARG_OPR }, { "ornot", OPRL(0x11,0x28), BASE, ARG_OPRL }, { "xor", OPR(0x11,0x40), BASE, ARG_OPR }, { "xor", OPRL(0x11,0x40), BASE, ARG_OPRL }, { "cmovlt", OPR(0x11,0x44), BASE, ARG_OPR }, { "cmovlt", OPRL(0x11,0x44), BASE, ARG_OPRL }, { "cmovge", OPR(0x11,0x46), BASE, ARG_OPR }, { "cmovge", OPRL(0x11,0x46), BASE, ARG_OPRL }, { "eqv", OPR(0x11,0x48), BASE, ARG_OPR }, { "eqv", OPRL(0x11,0x48), BASE, ARG_OPRL }, { "xornot", OPR(0x11,0x48), BASE, ARG_OPR }, /* alias */ { "xornot", OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */ { "amask", OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */ { "amask", OPRL(0x11,0x61), BASE, ARG_OPRLZ1 }, /* ev56 but */ { "cmovle", OPR(0x11,0x64), BASE, ARG_OPR }, { "cmovle", OPRL(0x11,0x64), BASE, ARG_OPRL }, { "cmovgt", OPR(0x11,0x66), BASE, ARG_OPR }, { "cmovgt", OPRL(0x11,0x66), BASE, ARG_OPRL }, { "implver", OPRL_(0x11,0x6C)|(31<<21)|(1<<13), 0xFFFFFFE0, BASE, { RC } }, /* ev56 but */ { "mskbl", OPR(0x12,0x02), BASE, ARG_OPR }, { "mskbl", OPRL(0x12,0x02), BASE, ARG_OPRL }, { "extbl", OPR(0x12,0x06), BASE, ARG_OPR }, { "extbl", OPRL(0x12,0x06), BASE, ARG_OPRL }, { "insbl", OPR(0x12,0x0B), BASE, ARG_OPR }, { "insbl", OPRL(0x12,0x0B), BASE, ARG_OPRL }, { "mskwl", OPR(0x12,0x12), BASE, ARG_OPR }, { "mskwl", OPRL(0x12,0x12), BASE, ARG_OPRL }, { "extwl", OPR(0x12,0x16), BASE, ARG_OPR }, { "extwl", OPRL(0x12,0x16), BASE, ARG_OPRL }, { "inswl", OPR(0x12,0x1B), BASE, ARG_OPR }, { "inswl", OPRL(0x12,0x1B), BASE, ARG_OPRL }, { "mskll", OPR(0x12,0x22), BASE, ARG_OPR }, { "mskll", OPRL(0x12,0x22), BASE, ARG_OPRL }, { "extll", OPR(0x12,0x26), BASE, ARG_OPR }, { "extll", OPRL(0x12,0x26), BASE, ARG_OPRL }, { "insll", OPR(0x12,0x2B), BASE, ARG_OPR }, { "insll", OPRL(0x12,0x2B), BASE, ARG_OPRL }, { "zap", OPR(0x12,0x30), BASE, ARG_OPR }, { "zap", OPRL(0x12,0x30), BASE, ARG_OPRL }, { "zapnot", OPR(0x12,0x31), BASE, ARG_OPR }, { "zapnot", OPRL(0x12,0x31), BASE, ARG_OPRL }, { "mskql", OPR(0x12,0x32), BASE, ARG_OPR }, { "mskql", OPRL(0x12,0x32), BASE, ARG_OPRL }, { "srl", OPR(0x12,0x34), BASE, ARG_OPR }, { "srl", OPRL(0x12,0x34), BASE, ARG_OPRL }, { "extql", OPR(0x12,0x36), BASE, ARG_OPR }, { "extql", OPRL(0x12,0x36), BASE, ARG_OPRL }, { "sll", OPR(0x12,0x39), BASE, ARG_OPR }, { "sll", OPRL(0x12,0x39), BASE, ARG_OPRL }, { "insql", OPR(0x12,0x3B), BASE, ARG_OPR }, { "insql", OPRL(0x12,0x3B), BASE, ARG_OPRL }, { "sra", OPR(0x12,0x3C), BASE, ARG_OPR }, { "sra", OPRL(0x12,0x3C), BASE, ARG_OPRL }, { "mskwh", OPR(0x12,0x52), BASE, ARG_OPR }, { "mskwh", OPRL(0x12,0x52), BASE, ARG_OPRL }, { "inswh", OPR(0x12,0x57), BASE, ARG_OPR }, { "inswh", OPRL(0x12,0x57), BASE, ARG_OPRL }, { "extwh", OPR(0x12,0x5A), BASE, ARG_OPR }, { "extwh", OPRL(0x12,0x5A), BASE, ARG_OPRL }, { "msklh", OPR(0x12,0x62), BASE, ARG_OPR }, { "msklh", OPRL(0x12,0x62), BASE, ARG_OPRL }, { "inslh", OPR(0x12,0x67), BASE, ARG_OPR }, { "inslh", OPRL(0x12,0x67), BASE, ARG_OPRL }, { "extlh", OPR(0x12,0x6A), BASE, ARG_OPR }, { "extlh", OPRL(0x12,0x6A), BASE, ARG_OPRL }, { "mskqh", OPR(0x12,0x72), BASE, ARG_OPR }, { "mskqh", OPRL(0x12,0x72), BASE, ARG_OPRL }, { "insqh", OPR(0x12,0x77), BASE, ARG_OPR }, { "insqh", OPRL(0x12,0x77), BASE, ARG_OPRL }, { "extqh", OPR(0x12,0x7A), BASE, ARG_OPR }, { "extqh", OPRL(0x12,0x7A), BASE, ARG_OPRL }, { "mull", OPR(0x13,0x00), BASE, ARG_OPR }, { "mull", OPRL(0x13,0x00), BASE, ARG_OPRL }, { "mulq", OPR(0x13,0x20), BASE, ARG_OPR }, { "mulq", OPRL(0x13,0x20), BASE, ARG_OPRL }, { "umulh", OPR(0x13,0x30), BASE, ARG_OPR },⌨️ 快捷键说明
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