📄 cpu.h.svn-base
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#define SPR_MPC_MD_CTR (0x308)#define SPR_PERF9 (0x309)#define SPR_RCPU_L2U_RBA1 (0x309)#define SPR_MPC_MD_CASID (0x309)#define SPR_PERFA (0x30A)#define SPR_RCPU_L2U_RBA2 (0x30A)#define SPR_MPC_MD_AP (0x30A)#define SPR_PERFB (0x30B)#define SPR_620_MMCR0R (0x30B)#define SPR_RCPU_L2U_RBA3 (0x30B)#define SPR_MPC_MD_EPN (0x30B)#define SPR_PERFC (0x30C)#define SPR_MPC_MD_TWB (0x30C)#define SPR_PERFD (0x30D)#define SPR_MPC_MD_TWC (0x30D)#define SPR_PERFE (0x30E)#define SPR_MPC_MD_RPN (0x30E)#define SPR_PERFF (0x30F)#define SPR_MPC_MD_TW (0x30F)#define SPR_UPERF0 (0x310)#define SPR_UPERF1 (0x311)#define SPR_UPERF2 (0x312)#define SPR_UPERF3 (0x313)#define SPR_620_PMC1W (0x313)#define SPR_UPERF4 (0x314)#define SPR_620_PMC2W (0x314)#define SPR_UPERF5 (0x315)#define SPR_UPERF6 (0x316)#define SPR_UPERF7 (0x317)#define SPR_UPERF8 (0x318)#define SPR_UPERF9 (0x319)#define SPR_UPERFA (0x31A)#define SPR_UPERFB (0x31B)#define SPR_620_MMCR0W (0x31B)#define SPR_UPERFC (0x31C)#define SPR_UPERFD (0x31D)#define SPR_UPERFE (0x31E)#define SPR_UPERFF (0x31F)#define SPR_RCPU_MI_RA0 (0x320)#define SPR_MPC_MI_DBCAM (0x320)#define SPR_RCPU_MI_RA1 (0x321)#define SPR_MPC_MI_DBRAM0 (0x321)#define SPR_RCPU_MI_RA2 (0x322)#define SPR_MPC_MI_DBRAM1 (0x322)#define SPR_RCPU_MI_RA3 (0x323)#define SPR_RCPU_L2U_RA0 (0x328)#define SPR_MPC_MD_DBCAM (0x328)#define SPR_RCPU_L2U_RA1 (0x329)#define SPR_MPC_MD_DBRAM0 (0x329)#define SPR_RCPU_L2U_RA2 (0x32A)#define SPR_MPC_MD_DBRAM1 (0x32A)#define SPR_RCPU_L2U_RA3 (0x32B)#define SPR_440_INV0 (0x370)#define SPR_440_INV1 (0x371)#define SPR_440_INV2 (0x372)#define SPR_440_INV3 (0x373)#define SPR_440_ITV0 (0x374)#define SPR_440_ITV1 (0x375)#define SPR_440_ITV2 (0x376)#define SPR_440_ITV3 (0x377)#define SPR_440_CCR1 (0x378)#define SPR_DCRIPR (0x37B)#define SPR_PPR (0x380)#define SPR_750_GQR0 (0x390)#define SPR_440_DNV0 (0x390)#define SPR_750_GQR1 (0x391)#define SPR_440_DNV1 (0x391)#define SPR_750_GQR2 (0x392)#define SPR_440_DNV2 (0x392)#define SPR_750_GQR3 (0x393)#define SPR_440_DNV3 (0x393)#define SPR_750_GQR4 (0x394)#define SPR_440_DTV0 (0x394)#define SPR_750_GQR5 (0x395)#define SPR_440_DTV1 (0x395)#define SPR_750_GQR6 (0x396)#define SPR_440_DTV2 (0x396)#define SPR_750_GQR7 (0x397)#define SPR_440_DTV3 (0x397)#define SPR_750_THRM4 (0x398)#define SPR_750CL_HID2 (0x398)#define SPR_440_DVLIM (0x398)#define SPR_750_WPAR (0x399)#define SPR_440_IVLIM (0x399)#define SPR_750_DMAU (0x39A)#define SPR_750_DMAL (0x39B)#define SPR_440_RSTCFG (0x39B)#define SPR_BOOKE_DCDBTRL (0x39C)#define SPR_BOOKE_DCDBTRH (0x39D)#define SPR_BOOKE_ICDBTRL (0x39E)#define SPR_BOOKE_ICDBTRH (0x39F)#define SPR_UMMCR2 (0x3A0)#define SPR_UPMC5 (0x3A1)#define SPR_UPMC6 (0x3A2)#define SPR_UBAMR (0x3A7)#define SPR_UMMCR0 (0x3A8)#define SPR_UPMC1 (0x3A9)#define SPR_UPMC2 (0x3AA)#define SPR_USIAR (0x3AB)#define SPR_UMMCR1 (0x3AC)#define SPR_UPMC3 (0x3AD)#define SPR_UPMC4 (0x3AE)#define SPR_USDA (0x3AF)#define SPR_40x_ZPR (0x3B0)#define SPR_BOOKE_MAS7 (0x3B0)#define SPR_620_PMR0 (0x3B0)#define SPR_MMCR2 (0x3B0)#define SPR_PMC5 (0x3B1)#define SPR_40x_PID (0x3B1)#define SPR_620_PMR1 (0x3B1)#define SPR_PMC6 (0x3B2)#define SPR_440_MMUCR (0x3B2)#define SPR_620_PMR2 (0x3B2)#define SPR_4xx_CCR0 (0x3B3)#define SPR_BOOKE_EPLC (0x3B3)#define SPR_620_PMR3 (0x3B3)#define SPR_405_IAC3 (0x3B4)#define SPR_BOOKE_EPSC (0x3B4)#define SPR_620_PMR4 (0x3B4)#define SPR_405_IAC4 (0x3B5)#define SPR_620_PMR5 (0x3B5)#define SPR_405_DVC1 (0x3B6)#define SPR_620_PMR6 (0x3B6)#define SPR_405_DVC2 (0x3B7)#define SPR_620_PMR7 (0x3B7)#define SPR_BAMR (0x3B7)#define SPR_MMCR0 (0x3B8)#define SPR_620_PMR8 (0x3B8)#define SPR_PMC1 (0x3B9)#define SPR_40x_SGR (0x3B9)#define SPR_620_PMR9 (0x3B9)#define SPR_PMC2 (0x3BA)#define SPR_40x_DCWR (0x3BA)#define SPR_620_PMRA (0x3BA)#define SPR_SIAR (0x3BB)#define SPR_405_SLER (0x3BB)#define SPR_620_PMRB (0x3BB)#define SPR_MMCR1 (0x3BC)#define SPR_405_SU0R (0x3BC)#define SPR_620_PMRC (0x3BC)#define SPR_401_SKR (0x3BC)#define SPR_PMC3 (0x3BD)#define SPR_405_DBCR1 (0x3BD)#define SPR_620_PMRD (0x3BD)#define SPR_PMC4 (0x3BE)#define SPR_620_PMRE (0x3BE)#define SPR_SDA (0x3BF)#define SPR_620_PMRF (0x3BF)#define SPR_403_VTBL (0x3CC)#define SPR_403_VTBU (0x3CD)#define SPR_DMISS (0x3D0)#define SPR_DCMP (0x3D1)#define SPR_HASH1 (0x3D2)#define SPR_HASH2 (0x3D3)#define SPR_BOOKE_ICDBDR (0x3D3)#define SPR_TLBMISS (0x3D4)#define SPR_IMISS (0x3D4)#define SPR_40x_ESR (0x3D4)#define SPR_PTEHI (0x3D5)#define SPR_ICMP (0x3D5)#define SPR_40x_DEAR (0x3D5)#define SPR_PTELO (0x3D6)#define SPR_RPA (0x3D6)#define SPR_40x_EVPR (0x3D6)#define SPR_L3PM (0x3D7)#define SPR_403_CDBCR (0x3D7)#define SPR_L3ITCR0 (0x3D8)#define SPR_TCR (0x3D8)#define SPR_40x_TSR (0x3D8)#define SPR_IBR (0x3DA)#define SPR_40x_TCR (0x3DA)#define SPR_ESASRR (0x3DB)#define SPR_40x_PIT (0x3DB)#define SPR_403_TBL (0x3DC)#define SPR_403_TBU (0x3DD)#define SPR_SEBR (0x3DE)#define SPR_40x_SRR2 (0x3DE)#define SPR_SER (0x3DF)#define SPR_40x_SRR3 (0x3DF)#define SPR_L3OHCR (0x3E8)#define SPR_L3ITCR1 (0x3E9)#define SPR_L3ITCR2 (0x3EA)#define SPR_L3ITCR3 (0x3EB)#define SPR_HID0 (0x3F0)#define SPR_40x_DBSR (0x3F0)#define SPR_HID1 (0x3F1)#define SPR_IABR (0x3F2)#define SPR_40x_DBCR0 (0x3F2)#define SPR_601_HID2 (0x3F2)#define SPR_Exxx_L1CSR0 (0x3F2)#define SPR_ICTRL (0x3F3)#define SPR_HID2 (0x3F3)#define SPR_750CL_HID4 (0x3F3)#define SPR_Exxx_L1CSR1 (0x3F3)#define SPR_440_DBDR (0x3F3)#define SPR_LDSTDB (0x3F4)#define SPR_750_TDCL (0x3F4)#define SPR_40x_IAC1 (0x3F4)#define SPR_MMUCSR0 (0x3F4)#define SPR_DABR (0x3F5)#define DABR_MASK (~(target_ulong)0x7)#define SPR_Exxx_BUCSR (0x3F5)#define SPR_40x_IAC2 (0x3F5)#define SPR_601_HID5 (0x3F5)#define SPR_40x_DAC1 (0x3F6)#define SPR_MSSCR0 (0x3F6)#define SPR_970_HID5 (0x3F6)#define SPR_MSSSR0 (0x3F7)#define SPR_MSSCR1 (0x3F7)#define SPR_DABRX (0x3F7)#define SPR_40x_DAC2 (0x3F7)#define SPR_MMUCFG (0x3F7)#define SPR_LDSTCR (0x3F8)#define SPR_L2PMCR (0x3F8)#define SPR_750FX_HID2 (0x3F8)#define SPR_620_BUSCSR (0x3F8)#define SPR_Exxx_L1FINV0 (0x3F8)#define SPR_L2CR (0x3F9)#define SPR_620_L2CR (0x3F9)#define SPR_L3CR (0x3FA)#define SPR_750_TDCH (0x3FA)#define SPR_IABR2 (0x3FA)#define SPR_40x_DCCR (0x3FA)#define SPR_620_L2SR (0x3FA)#define SPR_ICTC (0x3FB)#define SPR_40x_ICCR (0x3FB)#define SPR_THRM1 (0x3FC)#define SPR_403_PBL1 (0x3FC)#define SPR_SP (0x3FD)#define SPR_THRM2 (0x3FD)#define SPR_403_PBU1 (0x3FD)#define SPR_604_HID13 (0x3FD)#define SPR_LT (0x3FE)#define SPR_THRM3 (0x3FE)#define SPR_RCPU_FPECR (0x3FE)#define SPR_403_PBL2 (0x3FE)#define SPR_PIR (0x3FF)#define SPR_403_PBU2 (0x3FF)#define SPR_601_HID15 (0x3FF)#define SPR_604_HID15 (0x3FF)#define SPR_E500_SVR (0x3FF)/*****************************************************************************//* Memory access type : * may be needed for precise access rights control and precise exceptions. */enum { /* 1 bit to define user level / supervisor access */ ACCESS_USER = 0x00, ACCESS_SUPER = 0x01, /* Type of instruction that generated the access */ ACCESS_CODE = 0x10, /* Code fetch access */ ACCESS_INT = 0x20, /* Integer load/store access */ ACCESS_FLOAT = 0x30, /* floating point load/store access */ ACCESS_RES = 0x40, /* load/store with reservation */ ACCESS_EXT = 0x50, /* external access */ ACCESS_CACHE = 0x60, /* Cache manipulation */};/* Hardware interruption sources: * all those exception can be raised simulteaneously *//* Input pins definitions */enum { /* 6xx bus input pins */ PPC6xx_INPUT_HRESET = 0, PPC6xx_INPUT_SRESET = 1, PPC6xx_INPUT_CKSTP_IN = 2, PPC6xx_INPUT_MCP = 3, PPC6xx_INPUT_SMI = 4, PPC6xx_INPUT_INT = 5, PPC6xx_INPUT_TBEN = 6, PPC6xx_INPUT_WAKEUP = 7, PPC6xx_INPUT_NB,};enum { /* Embedded PowerPC input pins */ PPCBookE_INPUT_HRESET = 0, PPCBookE_INPUT_SRESET = 1, PPCBookE_INPUT_CKSTP_IN = 2, PPCBookE_INPUT_MCP = 3, PPCBookE_INPUT_SMI = 4, PPCBookE_INPUT_INT = 5, PPCBookE_INPUT_CINT = 6, PPCBookE_INPUT_NB,};enum { /* PowerPC 40x input pins */ PPC40x_INPUT_RESET_CORE = 0, PPC40x_INPUT_RESET_CHIP = 1, PPC40x_INPUT_RESET_SYS = 2, PPC40x_INPUT_CINT = 3, PPC40x_INPUT_INT = 4, PPC40x_INPUT_HALT = 5, PPC40x_INPUT_DEBUG = 6, PPC40x_INPUT_NB,};enum { /* RCPU input pins */ PPCRCPU_INPUT_PORESET = 0, PPCRCPU_INPUT_HRESET = 1, PPCRCPU_INPUT_SRESET = 2, PPCRCPU_INPUT_IRQ0 = 3, PPCRCPU_INPUT_IRQ1 = 4, PPCRCPU_INPUT_IRQ2 = 5, PPCRCPU_INPUT_IRQ3 = 6, PPCRCPU_INPUT_IRQ4 = 7, PPCRCPU_INPUT_IRQ5 = 8, PPCRCPU_INPUT_IRQ6 = 9, PPCRCPU_INPUT_IRQ7 = 10, PPCRCPU_INPUT_NB,};#if defined(TARGET_PPC64)enum { /* PowerPC 970 input pins */ PPC970_INPUT_HRESET = 0, PPC970_INPUT_SRESET = 1, PPC970_INPUT_CKSTP = 2, PPC970_INPUT_TBEN = 3, PPC970_INPUT_MCP = 4, PPC970_INPUT_INT = 5, PPC970_INPUT_THINT = 6, PPC970_INPUT_NB,};#endif/* Hardware exceptions definitions */enum { /* External hardware exception sources */ PPC_INTERRUPT_RESET = 0, /* Reset exception */ PPC_INTERRUPT_WAKEUP, /* Wakeup exception */ PPC_INTERRUPT_MCK, /* Machine check exception */ PPC_INTERRUPT_EXT, /* External interrupt */ PPC_INTERRUPT_SMI, /* System management interrupt */ PPC_INTERRUPT_CEXT, /* Critical external interrupt */ PPC_INTERRUPT_DEBUG, /* External debug exception */ PPC_INTERRUPT_THERM, /* Thermal exception */ /* Internal hardware exception sources */ PPC_INTERRUPT_DECR, /* Decrementer exception */ PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */ PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */ PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */ PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */ PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */ PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */ PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */};/*****************************************************************************/#endif /* !defined (__CPU_PPC_H__) */⌨️ 快捷键说明
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